Semiconductor memory device with memory cells operated by boosted voltage

A semiconductor memory device, comprising:

• a plurality of static memory cells each comprising N-channel first and second driver MOS transistors, N-channel first and second transfer MOS transistors, and P-channel first and second load MOS transistors, and being placed in an array on a semiconductor substrate,
• wherein source electrodes of the driver MOS transistors are coupled to a first operating potential node, and source electrodes of the first and second load MOS transistors are coupled to a second operating potential node,
• wherein during a write operation, a potential difference between the first operating potential node and the second operating potential node is larger than a high-level potential applied to gate electrodes of the first and second transfer MOS transistors,
• wherein the first driver MOS transistor and the first transfer MOS transistor are formed in a first P-well region,
• wherein the second driver MOS transistor and the second transfer MOS transistor are formed in a second P-well region,
• wherein the first and second P-channel load MOS transistors are formed in a first N-well region, which is between the first and second P-well regions,
• wherein a center line of diffusion layers of the first driver MOS transistor and the first transfer MOS transistor is parallel to a boundary between the first P-well region and said first N-well region
• outer shapes of said diffusion layers are linearly symmetric against the center line, and
• the gate width size of the N-channel driver MOS transistors is not more than 1.4 times the gate width size of the N-channel type transfer MOS transistors.