US 6,791,882 B2Granted

Nonvolatile semiconductor memory device

AssigneeRenesas Technology Corp.

InventorsKoichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume

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Abstract

An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.

Claims20

Dependent claims

A processing apparatus comprising:

a central processing unit;
a nonvolatile memory;
a volatile memory;
a liquid crystal display;
an input/output port;
and
a bus,
wherein said central processing unit is capable of designating either one of an erase operation and a program operation to said nonvolatile memory, via said bus, such that (i) when said erase operation is designated, said nonvolatile memory erases data stored therein, and (ii) when said program operation is designated, said nonvolatile memory stores data therein,
wherein said erase operation includes a threshold voltage moving operation and a verily operation,
wherein said threshold voltage moving operation is that in which a threshold voltage of a memory call in said nonvolatile memory is moved to a threshold voltage range indicating an erase state,
wherein said verify operation determines whether the threshold voltage moving operation of said memory cell to said erase state is completed,
wherein said nonvolatile memory repeats said erase operation when the threshold voltage moving operation of said memory cell to that of an erase state is not yet completed, the erase operation of said nonvolatile memory ending when the threshold voltage of said memory cell is indicative of said erase state, and
wherein said nonvolatile memory is capable of freeing terminals coupled to said bus and said central processing unit is capable of accessing other component parts of said processing apparatus, via said bus, when said erase operation of data stored in said nonvolatile memory is being performed.

10 more elements

A processing apparatus comprising:

a central processing unit;
a flash memory;
a random access memory;
an input/output part;
and
a communication link through which a communication link-up is effected of said central processing unit, said flash memory, said random access memory and said input/output port,
wherein said central processing unit is capable of designating either one of an erase operation and a program operation to said flash memory,
wherein said erase operation includes a threshold voltage moving operation and a verify operation,
wherein said threshold voltage moving operation is that in which a threshold voltage of a memory cell in said flash memory is moved to a threshold voltage range indicating an erase state,
wherein said verify operation determines whether the threshold voltage moving operation of said memory cell to said erase state is completed,
wherein said flash memory repeats said erase operation when the threshold voltage moving operation of said memory cell to that of an erase state is not yet completed, the erase operation of said flash memory ending when the threshold voltage of said memory cell is indicative of said erase state,
wherein said flash memory is capable of freeing terminals coupled to said communication link when performing said erase operation, and
wherein said central processing unit is capable of accessing either one of said random access memory and said input/output port when said erase operation is being performed in said flash memory.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/175,958Filed 21 Jun 2002 · continuation
Priority: JP 1-272716 Feb 1989
Published: US 2002/0176282 A128 Nov 2002
Granted: 14 Sep 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/3445
Arrangements for verifying correct erasure or for detecting overerased cells: circuits or methods to verify correct erasure of nonvolatile memory…
G11C 16/06
Electrically programmable: auxiliary circuits, e.g. for writing into memory
G11C 16/12
Programming or data input circuits: programming voltage switching circuits
G11C 16/16
Circuits for erasing electrically, e.g. erase voltage switching circuits: for erasing blocks, e.g. arrays, words, groups

Family

Application07/474,994Parent of this continuation · filed 5 Feb 1990
Application07/567,391Parent of this continuation · filed 14 Aug 1990
Application07/888,447Parent of this continuation-in-part · filed 28 May 1992
Application08/144,500Parent of this continuation-in-part · filed 2 Nov 1993
Application08/249,899Parent of this continuation · filed 26 May 1994
Application08/456,797Parent of this continuation · filed 1 Jun 1995
Application08/720,060Parent of this continuation · filed 27 Sep 1996
Application09/425,041Parent of this continuation · filed 19 Oct 1999
Application09/829,053Parent of this continuation · filed 10 Apr 2001
US 2002/0176282 A1Pre-grant publication · published 28 Nov 2002
US 6,438,036 B2Parent of this continuation
US 6,259,629 B1Parent of this continuation
US 6,016,273 AParent of this continuation
US 5,781,476 AParent of this continuation
US 5,844,842 AParent of this continuation
Application08/249,899Parent of this continuation-in-part
Application08/144,500Parent of this continuation
Application07/474,994Parent of this continuation-in-part
Application07/888,447Parent of this continuation
US 2001/0030889 A1Published application
US 6,791,882 B2This patent

From the US filing history. Foreign family members aren’t listed.