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US 6,790,336 B2Granted
Method of fabricating damascene structures in mechanically weak interlayer dielectrics
AssigneeIntel Corporation
InventorTatyana Andryushchenko
Life of this patent
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Abstract
A copper damascene process for a mechanically weak low k dielectric layer is described. Electropolishing is used to etch back the copper. A sacrificial conductive layer beneath the barrier layer assures complete planarization of the copper.
Claims20
A damascene process comprising:
- depositing a dielectric;
- forming a sacrificial metal layer on the dielectric;
- forming an opening through the sacrificial metal layer into the dielectric;
- forming a barrier layer over the sacrificial metal layer and in the opening to line the opening;
- forming copper over the barrier layer;
- electropolishing the copper layer;
- removing the barrier layer;
- and
- removing the sacrificial metal layer with a chemical etchant that discriminates between the dielectric and the sacrificial metal layer.
6 more elements
In the fabrication of a damascene interconnect layer, the improvement comprising:
- forming a sacrificial metal layer on the surface of a dielectric prior to etching trenches in the dielectric;
- forming trenches in the dielectric;
- forming a barrier metal over the sacrificial metal layer so as to line the trenches with the barrier metal;
- forming copper over the barrier metal layer;
- and
- electropolishing the copper layer.
3 more elements
An interlayer dielectric forming process comprising:
- depositing a dielectric layer;
- forming a conductive layer on the dielectric layer;
- forming trenches in the dielectric layer through the conductive layer;
- forming barrier and copper layers over the conductive layer and in the trenches;
- and
- electropolishing the copper layer so as to form a damascene structure.
3 more elements
Dependencies are inferred from the claim text.