US 6,789,248 B1 · Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization

Abstract

A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments. The time delay resulting from the physical interconnects is extracted from the timing analysis of the electronic device and from the timing estimate performed during the physical synthesis. The time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis is then compared. The resistance and capacitance unit values used during the timing synthesis are then adjusted. The calibration is repeatedly executed until time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis are correlated.

Claims23

Dependent claims

A resistance and capacitance unit value calibration method employed in a synthesis of an electronic device comprising the steps of:

a) performing a synthesis of a preliminary description of said electronic device to form a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits;
b) performing a placing of said component circuits to create a listing describing physical locations of said component circuits within said electronic device;
c) performing a routing of said interconnections to create a listing describing a network of physical wire segments that form each interconnection of the component circuits;
d) performing a timing analysis of said electronic device to determine delay created by the component circuit and the networks of physical wire segments;
e) extracting a physical interconnect delay from the timing analysis of said electronic device;
f) extracting an estimated interconnect delay from a timing estimate performed during the timing synthesis;
g) comparing the physical interconnect delay with the estimated interconnect delay;
h) determining a resistance and capacitance unit error value;
i) adjusting the resistance and capacitance unit values used during the timing synthesis with said resistance and capacitance unit error value to calibrate said resistance and capacitance unit values;
and
j) reiterating steps a) through i) until the physical interconnect delay and the estimated interconnect delay are correlated.

8 more elements

A method for designing an electronic device comprising the steps of:

creating a preliminary description of said electronic device including constraints to be employed for said designing;
calibrating resistance and capacitance unit values employed in a synthesis of an electronic device by the steps of:
a) performing a synthesis of the preliminary description of said electronic device to form a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits,
b) performing a placing of said component circuits to create a listing describing physical locations of said component circuits within said electronic device,
c) performing a routing of said interconnections to create a listing describing a network of physical wire segments that form each interconnection of the component circuits,
d) performing a timing analysis of said electronic device to determine delay created by the component circuit and the networks of physical wire segments,
e) extracting a physical interconnect delay from the timing analysis of said electronic device,
f) extracting an estimated interconnect delay from a timing estimate performed during the timing synthesis,
g) comparing the physical interconnect delay with the estimated interconnect delay,
h) determining a resistance and capacitance unit error value,
i) adjusting the resistance and capacitance unit values used during the timing synthesis with said resistance and capacitance unit error value to calibrate said resistance and capacitance unit values, and
j) reiterating steps a) through i) until the physical interconnect delay and the estimated interconnect delay are correlated,
performing a synthesis of the preliminary description of said electronic device to form a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits;
performing a placing of said component circuits to create a listing describing physical locations of said component circuits within said electronic device;
performing a routing of said inter connections to create a listing describing a network of physical wire segments that form each interconnection of the component circuits;
verifying that the design of the electronic device adheres to the preliminary description of the electronic device;
and
if the design of the electronic device adheres to the preliminary description of the electronic device, transferring said design for fabrication.

15 more elements

An apparatus for designing an electronic device comprising:

means for creating a preliminary description of said electronic device including constraints to be employed for said designing;
means for calibrating resistance and capacitance unit values employed in a synthesis of an electronic device comprising:
a) means for performing a synthesis of the preliminary description of said electronic device to form a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits,
b) means for performing a placing of said component circuits to create a listing describing physical locations of said component circuits within said electronic device,
c) means for performing a routing of said interconnections to create a listing describing a network of physical wire segments that form each interconnection of the component circuits,
d) means for performing a timing analysis of said electronic device to determine delay created by the component circuit and the networks of physical wire segments,
e) means for extracting a physical interconnect delay from the timing analysis of said electronic device,
f) means for extracting an estimated interconnect delay from a timing estimate performed during the timing synthesis,
g) means for comparing the physical interconnect delay with the estimated interconnect delay,
h) means for determining a resistance and capacitance unit error value,
i) means for adjusting the resistance and capacitance unit values used during the timing synthesis with said resistance and capacitance unit error value to calibrate said resistance and capacitance unit values, and
j) means for repetitively executing the means of a) through i) until the physical interconnect delay and the estimated interconnect delay are correlated;
means for performing a synthesis of the preliminary description of said electronic device to form a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits;
means for performing a placing of said component circuits to create a listing describing physical locations of said component circuits within said electronic device;
means for performing a routing of said interconnections to create a listing describing a network of physical wire segments that form each interconnection of the component circuits;
means for verifying that the design of the electronic device adheres to the preliminary description of the electronic device;
and
means for transferring said design for fabrication, which are operable if the design of the electronic device adheres to the preliminary description of the electronic device.

15 more elements

An electronic device design automation system comprising:

a design data retaining device containing a preliminary description of an electronic device;
a library data device containing a listing of electrical components usable within said electronic device, a listing of physical parameters for said electrical components and a listing of constraints to be employed for designing and fabricating said electronic device, wherein said listing of physical parameters includes resistance and capacitance unit values;
a physical synthesizer in communication with the design retaining device and the library retaining device to receive the preliminary description of the electronic device and from the listing of electrical components usable within said electronic device, the listing of physical parameters for said electrical components and the listing of constraints to be employed for designing and fabricating said electronic device generates a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits;
an electrical component placing apparatus in communication with the physical synthesizer to receive the listing of the component circuits and to create a physical arrangement said component circuits,
a wire routing apparatus in communication with the physical synthesizer and the electrical component placing apparatus to receive the listing of the component circuits and the physical arrangement of the component circuits to create an interconnection listing describing all physical interconnections between the electrical components;
a resistance and capacitance extraction apparatus in communication with the wire routing apparatus to determine a resistance value and a capacitance value for each unit segment of each physical interconnection between the electrical components;
a timing analyzer in communication with the physical synthesizer to receive the listing of electrical components and the wire routing apparatus to receive the physical interconnections between the electrical components to determine a timing analysis describing actual delays of signals propagated through the electrical components and the interconnections of the electrical components;
and
an unit resistance and capacitance value calibration apparatus in communication with the physical synthesizer to receive a preliminary timing estimate, with the timing analyzer to receive the timing analysis, and with the resistance and capacitance extraction apparatus to receive the resistance value and the capacitance value for each unit segment of each physical interconnection between the electrical components, said resistance adjustment apparatus compares the preliminary timing estimate with the timing analysis and from the resistance value and the capacitance value of each segment of the physical interconnections derives an unit resistance adjustment factor and an unit capacitance adjustment factor to correct the resistance and capacitance unit values in the library data devices;
wherein said electronic device design automation system is operated repetitively until the preliminary timing estimate and the timing analysis are correlated, at which time said electronic device is design and if meeting a design specification for said electronic device, said electronic device is fabricated.

7 more elements

A medium for retaining a computer program which, when executed on a computing system, calibrates resistance and capacitance unit values employed in a synthesis of an electronic device, said computer program comprising the steps of:

a) performing a synthesis of preliminary description of said electronic device to form a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits;
b) performing a placing of said component circuits to create a listing describing physical locations of said component circuits within said electronic device;
c) performing a routing of said interconnections to create a listing describing a network of physical wire segments that form each interconnection of the component circuits;
d) performing a timing analysis of said electronic device to determine delay created by the component circuit and the networks of physical wire segments;
e) extracting a physical interconnect delay from the timing analysis of said electronic device;
f) extracting an estimated interconnect delay from a timing estimate performed during the timing synthesis;
g) comparing the physical interconnect delay with the estimated interconnect delay;
h) determining a resistance and capacitance unit error value;
i) adjusting the resistance and capacitance unit values used during the timing synthesis with said resistance and capacitance unit error value to calibrate said resistance and capacitance unit values;
and
j) reiterating steps a) through i) until the physical interconnect delay and the estimated interconnect delay are correlated.

8 more elements

A medium for retaining a computer program which, when executed on a computing system, automates a designing of an electronic device, said computer program comprising the steps of:

creating a preliminary description of said electronic device including constraints to be employed for said designing;
calibrating resistance and capacitance unit values employed in a synthesis of an electronic device by the steps of:
a) performing a synthesis of the preliminary description of said electronic device to form a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits,
b) performing a placing of said component circuits to create a listing describing physical locations of said component circuits within said electronic device,
c) performing a routing of said interconnections to create a listing describing a network of physical wire segments that form each interconnection of the component circuits,
d) performing a timing analysis of said electronic device to determine delay created by the component circuit and the networks of physical wire segments,
e) extracting a physical interconnect delay from the timing analysis of said electronic device,
f) extracting an estimated interconnect delay from a timing estimate performed during the timing synthesis,
g) comparing the physical interconnect delay with the estimated interconnect delay,
h) determining a resistance and capacitance unit error value,
i) adjusting the resistance and capacitance unit values used during the timing synthesis with said resistance and capacitance unit error value to calibrate said resistance and capacitance unit values, and
j) reiterating steps a) through i) until the physical interconnect delay and the estimated interconnect delay are correlated;
performing a synthesis of the preliminary description of said electronic device to form a listing of component circuits of said electronic device including a listing of interconnections of said electronic devices, said synthesis using said resistance and capacitance unit values to determine said listing of the component circuits;
performing a placing of said component circuits to create a listing describing physical locations of said component circuits within said electronic device;
performing a routing of said interconnections to create a listing describing a network of physical wire segments that form each interconnection of the component circuits;
verifying that the design of the electronic device adheres to the preliminary description of the electronic device;
and
if the design of the electronic device adheres to the preliminary description of the electronic device, transferring said design for fabrication.

15 more elements

Dependencies are inferred from the claim text.

Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization

Life of this patent

Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization

Life of this patent

Abstract

Claims23