Placement of clock objects under constraints

A method for placing a design onto an integrated circuit, said design comprising a plurality of electronic components, each of said electronic components being driven by at least one of a plurality of clocks, said method comprising:

• dividing said integrated circuit into a plurality of regions;
• generating a global placement solution for said design;
• identifying plural sets of said clocks for said regions based on said placement solution, said plural sets of said clocks being under a constraint;
• setting up a flow network representing said regions and said plural sets of clocks, wherein said flow network comprises a plurality of sources representing at least some of said plurality of clocks, a plurality of sinks representing at least some of said plurality of regions, and a plurality of edges connecting said sources and said sinks, and wherein at least one of said edges is associated with an initial cost, and said initial cost is related to deviation from said global placement solution;
• obtaining a flow solution for said flow network;
• and
• if said flow solution is infeasible, modifying said network to discourage said infeasible solution and repeating said obtaining step.