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AssigneeInternational Business Machines Corporation
InventorsJean-Paul Aldebert, Jean Calvignac, Fabrice Verplanken
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A method and system for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer. The method includes first in creating timing diagrams identifying the elements of the circuit and their time based interconnections. The method further comprises a translation of the timing based diagram editor files into HDL statement. The preferred embodiment is described, it comprises the use of an ASCII editor and a translation program to VHDL statements. A system is also described implementing the steps of the method in a computer. In order to avoid having different tools to translate timing based diagram editor files into HDL statements, a first step translating graphical editor output file into a PostScript file is performed by executing the “print to file” command of the printing driver of the computer. The PostScript file is then translated into a bitmap file using a RIP. The translation is then performed from the bitmap file into the HDL statements. This translation is “universal” as it can be used for any type of initial graphical file containing the timing diagram.
A method for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer, said method comprising the steps of:
A method for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer, said method comprising the step of:
A method for creating on a computer a timing base representation of an integrated circuit using a graphical editor operating on the computer, said method comprising the step of:
Dependencies are inferred from the claim text.