Method for optimizing test development for digital circuits
AssigneeR. Scott Fetherston
InventorR. Scott Fetherson
Life of this patent
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Abstract
The invention reduces test development time for a circuit by determining the longest delay through each circuit element input and output pin. The delays are determined by calculating a delay value metric for each input pin and output pin and by assigning a delay value metric to the respective pin. Branch depth and branch width values are calculated for each input and output pin, and branch width and branch depth values are assigned to the respective pin. A least slack path is determined from the delay metric values. A fault model defines criteria for detection of faults at each circuit element pin using a test vector and associates a delay with each detected fault. The fault model enables detection of more than a single fault by a test vector.
Claims27
A method to produce a set of vectors for use in testing a digital integrated circuit (IC) having a plurality of gates, each gate having at least one input pin and one output pin, each said pin definable as a fault site and said IC is definable as having branch depths and branch widths, the method comprising:
- for each said fault site, determining a delay metric that identifies the longest delay accumulated in a forward direction and in a reverse direction through said IC;
- wherein said delay metric is obtained by calculating and assigning an accumulated forward direction delay value and an accumulated reverse direction delay value through each said fault site for each said gate;
- for each said fault site, summing accumulated forward direction delay value and reverse direction delay value to provide a measure of maximum delay through each said fault site in said IC;
- wherein data associated with said measure of maximum delay is useable to define a longest physical path through said IC associated with said maximum delay;
- and
- iteratively using a set of longest physical paths defined by said measure of maximum delay to generate said set of vectors;
- wherein said set of vectors is useable by a tester apparatus to physically test said IC.
A method to acquire raw data for a digital integrated circuit (IC) having a plurality of gates, each gate having at least one input pin and one output pin, each said pin definable as a fault site, the method comprising:
- for each said fault site, determining a delay metric that identifies the longest delay accumulated in a forward direction and in a reverse direction through said IC;
- storing each said delay metric so determined;
- wherein data included in stored delay metrics permits determining longest physical paths through said fault sites in said IC without incurring excessive runtime analysis.
A computer readable medium wherein is stored a computer routine that upon execution by a computer system produces a set of vectors for use in testing a digital integrated circuit (IC) having a plurality of gates, each gate having at least one input pin and one output pin, each said pin definable as a fault site and said IC is definable as having branch depths and branch widths, the computer routine upon execution carrying out the following steps:
- for each said fault site, determining a delay metric that identifies the longest delay accumulated in a forward direction and in a reverse direction through said IC;
- wherein said delay metric is obtained by calculating and assigning an accumulated forward direction delay value and an accumulated reverse direction delay value through each said fault site for each said gate;
- for each said fault site, summing accumulated forward direction delay value and reverse direction delay value to provide a measure of maximum delay through each said fault site in said IC;
- wherein data associated with said measure of maximum delay is useable to define a longest physical path through said IC associated with said maximum delay;
- and
- iteratively using a set of longest physical paths defined by said measure of maximum delay to generate said set of vectors;
- wherein said set of vectors is useable by a tester apparatus to physically test said IC.
A computer readable medium wherein is stored a computer routine that upon execution by a computer system acquires raw data for a digital integrated circuit (IC) having a plurality of gates, each gate having at least one input pin and one output pin, each said pin definable as a fault site, the computer routine upon execution carrying out the following steps:
- for each said fault site, determining a delay metric that identifies the longest delay accumulated in a forward direction and in a reverse direction through said IC;
- storing each said delay metric so determined;
- wherein data included in stored delay metrics permits determining longest physical paths through said fault sites in said IC without incurring excessive runtime analysis.
An apparatus to produce a set of vectors for use in testing a digital integrated circuit (IC) having a plurality of gates, each gate having at least one input pin and one output pin, each said pin definable as a fault site and said IC definable as having branch depths and branch widths, the apparatus including:
- for each said fault site, means for determining a delay metric that identifies the longest delay accumulated in a forward direction and in a reverse direction through said IC;
- wherein said delay metric is obtained by calculating and assigning an accumulated forward direction delay value and an accumulated reverse direction delay value through each said fault site for each said gate;
- for each said fault site, means for summing accumulated forward direction delay value and reverse direction delay value to provide a measure of maximum delay through each said fault site in said IC;
- wherein data associated with said measure of maximum delay is useable to define a longest physical path through said IC associated with said maximum delay;
- and
- means for iteratively using a set of longest physical paths defined by said measure of maximum delay to generate said set of vectors;
- wherein said set of vectors is useable by a tester apparatus to physically test said IC.
Dependencies are inferred from the claim text.