Integrated circuit with self-test circuit

Abstract

In an integrated circuit comprising an application circuit (1) to be tested and a self-test circuit (5-16) which is provided for testing the application circuit (1) and comprises an arrangement (5-9) for generating deterministic test samples which are applied to the application circuit (1) for test purposes, the output signals occurring due to the application circuit (1) in dependence upon the test samples being evaluated by means of a signature register (13), an unlimited ON-chip testing possibility of the integrated circuit without additional circuit elements in the application circuit (1) is ensured for test purposes in that the self-test circuit (5-16) comprises a masking logic element (14) which, during testing, blocks those bits of the output signals of the application circuit (1) which, based on the circuit structure of the application circuit (1), have undefined states and applies only the other bits to the signature register (13).

Dependencies are inferred from the claim text.