System and method for allocating logic analyzer hardware resources

A plurality of hardware modules for use in a logic analyzer, each said hardware module connected to a plurality of data channels over which logic signals travel, comprising:

• a plurality of hardware event resources each configured to determine whether a specified event has occurred;
• a plurality of programmable event combiners operatively connected to each other and to each of the plurality of hardware event resources, configured to evaluate a programmed Boolean combination of a plurality of signals generated by a programmed combination of said plurality of hardware event resources, said event combiners implementing a branch condition statement of a trigger branch in a trigger sequence;
• an occurrence counter that determines whether said branch condition statement evaluates as being true for a programmed number of occurrences, and
• an action decoder, responsive to said occurrence counter, configure to invoke said event resources to implement one or more actions in an action list of said trigger branch in said trigger sequence.

A method for translating a branch condition statement of a trigger sequence in a logic analyzer including a plurality of hardware modules each connected to a plurality of data channels over which logic signals travel, the hardware modules including a plurality of hardware event resources configured to determine whether a specified event has occurred, and a plurality of programmable look-up table (LUT) event combiners configured to evaluate a programmed Boolean combination of a plurality of signals generated by a programmed combination of said plurality of hardware event resources, said event combiners implementing a branch condition statement of a trigger branch in a trigger sequence, the method comprising the steps of:

• expanding said branch condition statement Boolean expression into sum-of-products form;
• allocating a hardware event resource to implement each event in said branch condition statement;
• reducing said branch condition statement based on events that always evaluate true or false;
• expanding said branch condition statement based on pattern or edge events that span multiple hardware modules such that said spanning events are expanded to multiple events that contain only data channels that can be assigned within a single one of the plurality of hardware modules;
• and
• populating the combiner LUTs required by each event such that combiners are implemented in a two-level hierarchical scheme with event resources generating values that are provided as inputs to pre-combiners which in turn generate outputs that are provided to a post-combiner.