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US 6,789,212 B1Granted
Basic cell for N-dimensional self-healing arrays
OwnerEdwin E. Klingmaninventor
Life of this patent
Estimating the term…
Abstract
A system is described capable of excising individual cells in an N-dimensional array and healing the array connectivity without manual intervention. Thus cells that fail can be deleted and the array remain viable, although possibly requiring re-synchronization procedures to be performed. The system allows either replacement of bad cells or bypassing of bad cells, with appropriate cost and operational differences. Both level sensitive and edge sensitive excision mechanisms are described and the consequences of each discussed. The invention applies to processor arrays with one cell per physical chip or many cells per chip, and handles uni-directional or bi-directional data flows, and is generally both interface independent and technology independent.
Claims44
An extended processor element for connection between an upstream processor element and a downstream processor element, the extended processor element comprising:
- a processing cell having an upstream interface and a downstream interface, said processing cell for performing processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal.
1 more element
An extended processor element for connection between an upstream processor element and a downstream processor element, the extended processor element comprising:
- a processing cell having an upstream interface and a downstream interface, said processing cell for performing processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal, and
- wherein the extended upstream and extended downstream interfaces each include a bidirectional bus and the upstream and downstream cell interfaces each include a bidirectional bus.
2 more elements
An extended processor element for connection between an upstream processor element and a downstream processor element, the extended processor element comprising:
- a processing cell having an upstream interface and a downstream interface, said processing cell for performing processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal, and
- wherein the extended upstream and extended downstream interfaces each include a bidirectional bus and the upstream and downstream cell interfaces each include an input and output bus.
2 more elements
An extended processor element for connecting to an upstream processor element and a downstream processor element, the extended processor element comprising:
- a processing cell having an upstream interface and a downstream interface, said cell for performing processing operations of the element;
- and
- reconnection circuitry having an extended upstream interface for connecting to the adjacent upstream processor element and an extended downstream interface for connecting to the adjacent downstream processor element, said reconnection circuitry for disconnecting said cell from the extended upstream and extended downstream interfaces when said cell is determined to be faulty and for connecting a healthy replacement cell to the extended upstream and extended downstream interfaces in place of the faulty cell.
A chain of processor elements, the chain comprising:
- a plurality of extended processor elements, an extended processor element connected only to a downstream processor element being the head of the chain, an extended processor element connected only to an upstream processor element being the tail of the chain;
- wherein each extended processor element has an extended upstream interface for connecting to an upstream processor element and an extended downstream interface for connecting to a downstream processor element;
- and
- wherein each extended processor element includes:
- a processing cell for carrying out the processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal.
5 more elements
A chain of processor elements, the chain comprising:
- a plurality of extended processor elements, an extended processor element connected only to a downstream processor element being the head of the chain, an extended processor element connected only to an upstream processor element being the tail of the chain;
- wherein each extended processor element has an extended upstream interface for connecting to an upstream processor element and an extended downstream interface for connecting to a downstream processor element;
- and
- wherein each extended processor element includes:
- a processing cell for carrying out the processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal;
- and
- wherein an upstream processor element removes said cell of an adjacent downstream processor element from the chain by making the select signal received by said bypass circuitry of the downstream processor element active.
7 more elements
A chain of processor elements, the chain comprising:
- a plurality of extended processor elements, an extended processor element connected only to a downstream processor element being the head of the chain, an extended processor element connected only to an upstream processor element being the tail of the chain;
- wherein each extended processor element has an extended upstream interface for connecting to an upstream processor element and an extended downstream interface for connecting to a downstream processor element;
- and
- wherein each extended processor element includes:
- a processing cell for carrying out the processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal;
- and
- wherein a downstream processor element removes said cell of an adjacent upstream processor element from the chain by making the select signal received by said bypass circuitry of the upstream processor element active.
7 more elements
A chain of processor elements, the chain comprising:
- a plurality of extended processor elements, an extended processor element connected only to a downstream processor element being the head of the chain, an extended processor element connected only to an upstream processor element being the tail of the chain;
- wherein each extended processor element has an extended upstream interface for connecting to an upstream processor element and an extended downstream interface for connecting to a downstream processor element;
- and
- wherein each extended processor element includes:
- a processing cell for carrying out the processing operations of the extended processor element, and bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal;
- wherein the extended upstream and extended downstream interfaces each include a downstream bypass request signal that traverses the chain;
- and
- wherein an upstream processor element can bypass a plurality of adjacent downstream processor elements by pulsing the downstream bypass request signal.
6 more elements
A chain of processor elements, the chain comprising:
- a plurality of extended processor elements, an extended processor element connected only to a downstream processor element being the head of the chain, an extended processor element connected only to an upstream processor element being the tail of the chain;
- wherein each extended processor element has an extended upstream interface for connecting to an upstream processor element and an extended downstream interface for connecting to a downstream processor element;
- and
- wherein each extended processor element includes:
- a processing cell for carrying out the processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal;
- wherein the extended upstream and extended downstream interfaces each include an upstream bypass request signal that traverses the chain;
- and
- wherein a downstream processor element can bypass a plurality of adjacent upstream processor elements by pulsing the upstream bypass request signal.
8 more elements
A chain of processor elements, the chain comprising:
- a plurality of extended processor elements, an extended processor element connected only to a downstream processor element being the head of the chain, an extended processor element connected only to an upstream processor element being the tail of the chain;
- wherein each extended processor element has an extended upstream interface for connecting to an upstream processor element and an extended downstream interface for connecting to a downstream processor element;
- and
- wherein each extended processor element includes:
- a processing cell for carrying out the processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal;
- wherein the extended downstream interface has a bypass signal that connects only to any adjacent downstream element;
- wherein the downstream bypass request signal of every other processor element starting at the head element in the chain is activated to cause each adjacent downstream processor element to be bypassed in a first phase, a second phase following upon the end of the first phase;
- and
- wherein the downstream bypass request signal of every other processor element starting at the downstream element immediately adjacent to the head element is activated to cause each adjacent downstream processor element to be bypassed in the second phase, the first phase following upon the end of the second phase, so that alternate phase operation of processor elements in the chain is achieved.
9 more elements
A chain of processor elements, the chain comprising:
- a plurality of extended processor elements, an extended processor element connected only to a downstream processor element being the head of the chain, an extended processor element connected only to an upstream processor element being the tail of the chain;
- wherein each extended processor element has an extended upstream interface for connecting to an upstream processor element and an extended downstream interface for connecting to a downstream processor element;
- and
- wherein each extended processor element includes:
- a processing cell for carrying out the processing operations of the extended processor element;
- and
- bypass circuitry for bypassing the processing cell, said bypass circuitry connected to at least one select line to receive a select signal and connected between the extended upstream interface and said cell upstream interface and between the extended downstream interface and cell downstream interface,
- wherein said bypass circuitry is operative to connect the extended upstream interface to the extended downstream interface in response to an active select signal, and to connect said cell upstream interface to the extended upstream interface and said cell downstream interface to the extended downstream interface in response to an inactive select signal;
- wherein the extended upstream interface has a bypass signal that connects only to any adjacent upstream element;
- wherein the upstream bypass request signal of every other processor element starting at the tail element in the chain is activated to cause each adjacent upstream processor element to be bypassed in a first phase, a second phase following upon the end of the first phase;
- and
- wherein the upstream bypass request signal of every other processor element starting at the upstream element immediately adjacent to the tail element is activated to cause each adjacent up stream processor element to be bypassed in the second phase, the first phase following upon the end of the second phase, so that alternate phase operation of processor elements in the chain is achieved.
9 more elements
In a chain of extended processor elements each having a processing cell for carrying out the processing operations of the extended processor element, and bypass circuitry to connect said cell to an extended upstream interface and an extended downstream interface of the extended processor element when said bypass circuitry is not activated, and to connect the extended upstream interface to the extended downstream interface when said bypass circuitry is activated, the chain being formed by connecting upstream and downstream interfaces to each other, a method of removing a processing cell from a processor element, the method comprising the steps of:
- receiving information indicating that testing is required of the upstream processor element;
- testing the upstream processor element to determine whether said cell of the upstream element responds correctly;
- and
- activating the upstream processor element bypass circuitry to connect the upstream interface to the downstream interface of the upstream processor element if the upstream processor element does not respond correctly.
1 more element
A method of operating a chain of extended processor elements in alternate phases, each element having a processing cell for carrying out the processing operations of the extended processor element, and bypass circuitry to connect said cell to an extended upstream interface and an extended downstream interface of the extended processor element when said bypass circuitry is not activated, and to connect the extended upstream interface to the extended downstream interface when said bypass circuitry is activated, the chain being formed by connecting upstream and downstream interfaces to each other, each extended upstream interface having a bypass request line connected to any adjacent upstream element, each extended downstream interface having a bypass request line connected to any adjacent downstream element, the method comprising the steps of:
- activating a signal on the downstream bypass request line by every other processor element to activate said bypass circuitry of the next adjacent downstream element in a first phase, a second phase following the end of the first phase;
- deactivating the signal on the downstream bypass request line by every other processor element to restore the element to normal operation in the second phase;
- and
- activating the signal on the downstream bypass request line by each processor element bypassed in the first phase to bypass the next adjacent downstream element in the second phase.
1 more element
A method of testing a processing cell of an extended processor element in a chain of extended processor elements, each element having a processing cell for carrying out the processing operations of the extended processor element, said cell including a test port, and bypass circuitry to connect said cell to an extended upstream interface and an extended downstream interface of the extended processor element when said bypass circuitry is not activated, and to connect the extended upstream interface to the extended downstream interface when said bypass circuitry is activated, said bypass circuitry including test circuitry, the chain being formed by connecting upstream and downstream interfaces to each other and having a head element and a tail element, the upstream and downstream interfaces having a bypass request line and a test enable line traversing the chain, the method comprising the steps of:
- if testing a processor element other than the element at the head of the chain, issuing one or more pulses on the test enable line to select the processor element for testing;
- and
- issuing a pulse on the bypass request line to activate said bypass circuitry of the selected element, the test circuitry operative to block the connection of the extended upstream interface to the extended downstream interface and enable the connection of the test port to the extended upstream interface;
- and
- if testing the head processor element, issuing a pulse on the bypass request line to activate said bypass circuitry of the head element, the test circuitry operative to block the connection of the extended upstream interface to the extended downstream interface and enable the connection of the test port to the extended upstream interface.
2 more elements
An extended processor element for connection between an upstream processor element and a downstream processor element, the extended processor element comprising:
- a processing cell having an upstream interface and a downstream interface for a first direction and having an upstream interface and a downstream interface for a second direction, said processing cell for performing processing operations of the extended processor element;
- and
- first bypass circuitry for bypassing the processing cell in a first direction, the first bypass circuitry connected to at least one select line to receive a select signal and connected between the extended first upstream interface and said cell first upstream interface and between the extended first downstream interface and cell first downstream interface,
- wherein said first bypass circuitry is operative to connect the extended first upstream interface to the extended first downstream interface in response to an active select signal, and to connect said cell first upstream interface to the extended first upstream interface and said cell first downstream interface to the extended first downstream interface in response to an inactive select signal;
- wherein the extended first upstream and extended first downstream interfaces each include an input and output bus and the first upstream and first downstream cell interfaces each include an input and output bus;
- and
- second bypass circuitry for bypassing the processing cell in a second direction, the second bypass circuitry connected to at least one select line to receive a select signal and connected between an extended second upstream interface and said cell second upstream interface and between an extended second downstream interface and cell second downstream interface,
- wherein the extended second upstream and extended second downstream interfaces in the second direction each include an input and output bus and the second upstream and second downstream cell interface each includes an input and output bus, and
- wherein said first and second bypass circuitry is each operative to connect the respective upstream interface to the respective extended downstream interface in response to an active select signal, and to connect said respective cell upstream interface to the respective extended upstream interface and said respective cell downstream interface to the respective extended downstream interface in response to an inactive select signal.
6 more elements
Dependencies are inferred from the claim text.