US 6,789,210 B2 · Data processing system having memory including mode register

Abstract

A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Claims7

Dependent claims

A data processing system comprising:

a first processing unit controlling said data processing system;
a second processing unit;
and
a memory including a mode register,
wherein said memory is provided with a plurality of data processing information including a plurality of commands utilized by said second processing unit, and the plurality of commands are provided from said first processing unit,
wherein said memory is able to operate with a clock provided from said second processing unit, and
wherein said second processing unit includes a memory interface circuit which provides a plurality of data signals, address signals and control signals to said memory, and sets a value to said mode register included in said memory.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/353,910Filed 30 Jan 2003 · continuation

Priority

JP 5-25804015 Oct 1993

Published

US 2003/0115496 A119 Jun 2003

Granted

7 Sep 2004

Term ends

Not estimatedThe source records don’t support an estimate.

Classification24 codes

G09G 5/393
Control of the bit-mapped memory: arrangements for updating the contents of the bit-mapped memory
G06F 1/04
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
G06F 12/0207
Addressing or allocation; Relocation: with multidimensional access, e.g. row/column, matrix

Family

Application08/317,130Parent of this division · filed 3 Oct 1994

Application08/940,632Parent of this continuation · filed 30 Sep 1997

Application09/357,374Parent of this continuation · filed 20 Jul 1999

Application09/583,721Parent of this continuation · filed 30 May 2000

Application09/879,045Parent of this continuation · filed 13 Jun 2001

Application10/216,179Parent of this continuation · filed 12 Aug 2002

US 2003/0115496 A1Pre-grant publication · published 19 Jun 2003

US 6,550,014 B2Parent of this continuation

US 6,466,221 B1Parent of this continuation

US 6,288,728 B1Parent of this continuation

US 6,097,404 AParent of this continuation

US 5,999,197 AParent of this continuation

Application08/940,632Parent of this division

US 5,713,011 AParent of this division

US 2002/0190992 A1Published application

US 6,789,210 B2This patent

From the US filing history. Foreign family members aren’t listed.

Data processing system having memory including mode register

Life of this patent

Data processing system having memory including mode register

Life of this patent

Abstract

Claims7