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US 6,789,187 B2Granted
Processor reset and instruction fetches
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsRavi P. Singh, Charles P. Roth, Ravi Kolagotla, Juan G. Revilla
Life of this patent
Estimating the term…
Abstract
In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.
Claims22
A method for resetting a processor comprising:
- entering a reset mode;
- loading an instruction memory associated with the processor;
- responsive to the reset mode and loading the instruction memory, sending an extended reset signal to a fetch unit of a pipeline, the extended reset signal having a longer duration than a reset signal;
- and
- responsive to the extended reset signal, suspending instruction fetches from the fetch unit of the pipeline to the instruction memory until the extended reset signal is de-asserted and the instruction memory is loaded.
2 more elements
A method comprising:
- receiving a reset signal at a processor;
- receiving an instruction memory loading signal at the processor;
- asserting an extended reset signal in the processor when the reset signal is received at the processor, the extended reset signal having a longer duration than the reset signal;
- and
- sending the extended reset signal to a fetch unit of a pipeline in the processor.
2 more elements
An apparatus comprising:
- a first input adapted to receive a reset signal;
- a second input adapted to receive an instruction memory loading signal;
- an output;
- and
- a circuit coupled to the first input, second input and output, adapted to provide an extended reset signal to the output based on the reset signal and the instruction memory loading signal, the circuit asserting the extended reset signal when the reset signal is received, the circuit clearing the extended reset signal when the instruction memory loading signal is cleared.
2 more elements
A system comprising:
- a first input adapted to receive a reset signal;
- a second input adapted to receive an instruction memory loading signal;
- an output;
- a circuit coupled to the first input, second input and output, adapted to provide an extended reset signal to the output based on the reset signal and the instruction memory loading signal, the circuit asserting the extended reset signal when the reset signal is received, the circuit clearing the extended reset signal when the instruction memory loading signal is cleared;
- and
- a volatile memory operative to store instructions;
- and
- a pipeline operative to fetch instructions from the volatile memory and operative to receive the extended reset signal.
5 more elements
Dependencies are inferred from the claim text.