Instruction address generation and tracking in a pipelined processor
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsRavi P. Singh, Charles P. Roth, Gregory A. Overkamp
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Abstract
In an embodiment, an address pipeline corresponding to an instruction pipeline in a processor, for example, a digital signal processor (DSP), may generate and track the instruction address of each instruction at each stage. The address pipeline may include program count (PC) generation logic to automatically calculate the PC of the next instruction based on the width of the current instruction for sequential program flow. The address pipeline may also track valid bits associated with each instruction and store the address of the oldest valid instruction for return to the original program flow after a disruptive event.
Claims20
A method for generating addresses for variable-width instructions in a pipeline including at least a decode stage and one or more subsequent pipeline stages, comprising:
- calculating a next sequential address from a stored address and an instruction width of a first instruction in the pipeline, wherein said calculating is performed in the decode stage;
- and
- selecting between a branch target address and said next sequential.
An apparatus, including instructions residing on a machine-readable medium, for use in generating addresses for variable-width instructions in a pipeline including at least a decode stage and one or more subsequent pipeline stages, the instructions causing the machine to:
- calculate a next sequential address from a stored address and an instruction width of a first instruction in the pipeline, wherein said next sequential address is calculated in the decode stage;
- and
- select between a branch target address and said next sequential address.
Apparatus for generating an address of an instruction in a pipeline including at least a decode stage and one or more subsequent pipeline stages, comprising:
- an instruction decoder to decode the instruction, said instruction having an instruction width;
- a selection circuit to select a branch target address over a first calculated address in response to a break in a program flow, said first calculated address being calculated in the decode stage;
- and
- an adder to add the instruction width of the instruction to the address selected by the selection circuit to generate a second calculated address.
A system comprising:
- a flash memory;
- and
- a processor coupled to the flash memory and including a pipeline including at least a decode stage and one or more subsequent pipeline stages, said processor being adapted to:
- calculate a next sequential address from a stored address and an instruction width of a first instruction in the pipeline, wherein said next sequential address is calculated in the decode stage;
- and
- select between a branch target address and said next sequential address.
Dependencies are inferred from the claim text.