Apparatus and method for activation of a digital signal processor in an idle mode for interprocessor transfer of signal groups in a digital signal processing unit

In a digital signal processing unit having a plurality of digital signal processors, a method of transferring signal groups between a first and a second digital signal processor, the method comprising:

• when the first digital signal requires a signal group stored in the second digital signal processor, generating a control signal in the direct memory access controller of the first digital signal processor;
• applying the control signal to the direct memory access unit of the second digital signal processor;
• and
• when the second digital signal processor is in an IDLE mode, providing a transition to an ACTIVE mode as a result of the application of the first control signal.

In a digital signal processing unit having a plurality of digital signal processors, the digital signal processors each having an ACTIVE mode and an IDLE mode, apparatus providing that a first digital signal processor can change a second digital signal processor from an IDLE mode to an ACTIVE mode, the apparatus comprising:

• a first clock control circuit in the direct memory access controller of the first digital signal processor generating first control signal in response to a predetermined condition;
• a second clock control circuit in the direct memory access controller of the second digital signal processor responsive to the first control signal for changing the second digital signal processor from an IDLE mode to an ACTIVE mode;
• and
• a conducting path from the first clock control circuit to the second clock control circuit for carrying the first control signal.