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US 6,789,180 B1Granted
Method and apparatus for mask and/or counter address registers readback on the address bus in synchronous single and multi-port memories
AssigneeCypress Semiconductor Corporation
InventorStefan-Cristian Rezeanu
Life of this patent
Estimating the term…
Abstract
An apparatus comprising a memory device and one or more control circuits. The memory device may be configured to store and retrieve data. The one or more control circuits may be configured to control access to the memory device. Each of the control circuits may be configured to provide a readback of an internal address value when in a first state and a readback of a mask value when in a second state.
Claims18
An apparatus comprising:
- A memory device configured to store and retrieve data;
- and
- One or more control circuits configured to control access to said memory device, wherein each of said control circuits is configured to present at an external interface (i) an internal address value when in a first state and (ii) a mask value when in a second state, wherein at least one of said internal address value and said mask value is configured to be presented to said external interface during a single clock cycle.
An apparatus comprising:
- means for generating an internal address value for a memory device based on an external address value received on an address bus;
- and
- means for driving to said address bus (i) said internal address value when in a first state and (ii) a mask value when in a second state, wherein at least one of said internal address value and said mask value is configured to be presented to said external interface during a single clock cycle.
A method for determining an internal address value and a mask value, comprising the steps of:
- (A) generating said internal address value from an external address value received at an external interface;
- and
- (B) driving to said external interface said internal address value when an a first state and said mask value when in a second state, wherein step (B) further comprises driving at least one of said internal address value and said mask value during a single clock cycle on said address bus.
Dependencies are inferred from the claim text.