US 6,789,179 B2 · Method and system for fast data access using a memory array

Abstract

First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

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Drawings

Claims27

Dependent claims

A method for reading a misaligned data variable from an array of memory cells, wherein a first portion of the misaligned data variable resides in one or more first memory cells relating to a first address, and wherein a second portion of the misaligned data variable resides in one or more second memory cells relating to a second address, the method comprising:

providing first address-selection information relating to the first address;
providing second address-selection information relating to the second address, wherein the second address is not equal to the first address, and wherein the first address-selection information and the second address-selection information are contemporaneously provided;
providing first read information;
providing second read information;
read enabling the one or more first memory cells based on the first address-selection information and first read information;
read enabling the one or more second memory cells based on the second address-selection information and second read information;
and
assembling the data variable from the first data portion of the one or more first enabled memory cells and the second data portion of the one or more second enabled memory cells.

5 more elements

A memory system that can write a misaligned data variable to an array of memory cells, comprising:

an address device that contemporaneously provides at least first address-selection information relating to a first memory address and second address-selection information relating to a second memory address, wherein the second address is not equal to the first address, wherein the address device further provides first write information and second write information;
first enabling circuits that write-enable one or more first memory cells relating to the first address based on the first address-selection information and first write information;
second enabling circuits that write-enable one or more second memory cells relating to the second address based on the second address-selection information and second write information;
and
a buffer circuitry that provides a first portion of the misaligned data variable to the first enabled memory cells, and further provides a second portion of the misaligned data variable to the second enabled memory cells.

2 more elements

Dependencies are inferred from the claim text.

Description5,409 words

Summary615 words

#1. Field of the Invention

#This invention relates to methods and systems for fast access of computer-based memories.

#2. Related Art

Brief description of the drawings8 figures

#The invention is described in detail with regard to the following figures, wherein like numerals reference like elements, and wherein:

#FIG. 1 is a block diagram of an exemplary system capable of accessing misaligned data in a single memory-access cycle;

#FIG. 2 depicts the location-enable device of the system of FIG. 1;

Detailed description4,653 words

#A frequent problem that arises with modem computer-based systems is that, while the widths of an available physical memory are fixed, the widths of various data types can vary. For example, a particular microcomputer may have a thirty-two bit-wide memory, but may be required to access and manipulate eight-bit, sixteen-bit and thirty-two bit data. One problem that can arise with such systems is that different variables can become misaligned with the address boundaries of the physical memories.

#For instance, a first data variable in a block of thirty-two bit-wide RAM may be a byte-wide variable while a second data variable may be a four-byte variable. As a result, the first data variable will occupy the first byte of a first memory location, while the second data variable will occupy the remaining three bytes of the first memory location plus the first byte of the next memory location. One unfortunate consequence of this situation is that a computer accessing the second data variable can take two separate memory-access cycles to either read or write the second variable.

#However, by providing a memory array that allows contemporaneous access to two consecutive memory locations, e.g., the first and second memory locations, and that can simultaneously receive an array of read/write enable signals for the various bytes of both the even and odd memory addresses of the memory array, the misaligned data variable can be written to or read from the memory array in a single memory-access cycle. Using the example immediately above, the second data variable (represented by data bytes {d3, d2, d1, d0}) is misaligned such that the low three data variable bytes {d2, d1, d0} must be written to or read from the high three bytes {b03, b02, b01} of memory location zero and the low data variable byte {d0} must be written to or read from to the low byte {b10} of memory location one. That is, data variable bytes {d3, d2, d1, d0} must be written to or read from memory bytes {b10, b03, b02, b01} respectively.

Facts

Application

10/178,269Filed 25 Jun 2002 · us provisional application

Priority

29 Jun 2001

Published

US 2003/0005255 A12 Jan 2003

Granted

7 Sep 2004

Term ended

15 Dec 2022

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 173 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification7 codes

G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G06F 13/4243
Being a memory bus: with synchronous protocol
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…

Timeline

29 Jun 2001Priority claimedParent application 60/301,435
25 Jun 2002Application filedUS 10/178,269
25 Jun 2002Assigned to Broadcom Corporationassignment of assignor's interest
2 Jan 2003PublishedUS 2003/0005255 A1
7 Sep 2004GrantedUS 6,789,179 B2
11 Feb 2016Assigned to Bank of America, N.A., AS Collateral Agentpatent security agreement
1 Feb 2017Assigned to Avago Technologies General IP (Singapore) Pte. Ltd.assignment of assignor's interest
3 Feb 2017Assigned to Broadcom Corporationtermination and release of security interest in patents
4 Oct 2018Assigned to Avago Technologies International Sales Pte. Limitedmerger
6 Mar 2019Assigned to Avago Technologies International Sales Pte. Limitedcorrective assignment to correct the execution date previously recorded at reel: 047196 frame: 0097. assignor(s) hereby confirms the merger.
15 Dec 2022Term endedEstimated, includes 173 days of adjustment

Method and system for fast data access using a memory array

Life of this patent

Method and system for fast data access using a memory array

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims27

Description5,409 words

Drawings

Classification7 codes

Life of this patent

Description5,409 words