Address release method, and common buffering device for ATM switching system which employs the same method

A common buffering device, comprising:

• a common buffer memory storing ATM (asynchronous transfer mode) cells;
• a write controller for setting a write address of said common buffer memory, at which an ATM cell to be transmitted to a specific line is to be written on the common buffer memory;
• a read controller for reading out said ATM cell from said write address in the common butter memory to transmit said read-out ATM cell to the corresponding specific line;
• a write control table for setting a plurality of lines to which the ATM cell written in said common butter memory is multicast;
• and
• a read control table for setting, each time said ATM cell is sent to each of said plurality of lines set in the write control table is read-out from the common buffer memory, a corresponding designation line to which said read-out ATM cell has been sent;
• wherein said write controller releases the write address in the common buffer memory, when the write controller compares die plurality of lines set for multicast in said write control table with said designation line to which said ATM cell has been sent and determines the plurality of lines coinciding with all the designation lines.

A common buffering device comprising;

• a common buffer memory storing ATM (asynchronous transfer mode) cells;
• a write controller for setting a write address of said common buffer memory at which an ATM cell which to be transmitted to a specific line is to be written on the common buffer memory;
• a read controller for reading said ATM cell from said write address in the common buffer memory to transmit said read-out ATM cell to corresponding specific line;
• a write control table for setting a plurality of lines to the ATM cell written in said common buffering device is multicast;
• a read control table for setting, each time said ATM cell is sent to each of said plurality of lines set in the write control table is road-out from the common buffer memory, a corresponding designation line to which said read-out ATM cell has been sent and determines the plurality of lines coinciding with all the designation lines;
• wherein said write controller releases the write address in the common buffer memory, when the write controller compares the plurality of lines set for the coinciding with all the designation lines transmitted;
• wherein said write controller comprises:
• a register in which are sequentially set data indicating a destination line for the transmission of said ATM cell which is read by said read controller;
• a bit map generator for reading an ATM cell written at the same address in said common buffer memory, and for generating a bit map which designates a transmission destination line;
• a comparator for performing a comparison of said bit map generated by said bit map generator with a corresponding highway line in said write control table, for which the same write address has been set;
• and
• a controller for, upon receipt of the result of said comparison, feeding back to said register said data indicating which transmission destination highway line has been read for said ATM cell, or for clearing the contents of said write control table.