Memory access device allowing simultaneous access

A memory access device comprising:

• a CPU as a first function device;
• a second function device;
• a memory to which address buses and data buses of said first and second function devices are connected, wherein memory address space of said memory is divided into a plurality of blocks and each block has continuous address areas, said memory comprising
• a memory cell having a first terminal and a second terminal;
• a first bit line connected to said first terminal;
• a second bit line connected to said second terminal;
• a sense amplifier connected to said first bit line and said second bit line, and amplifying a voltage read out from said memory cell;
• and
• a write circuit connected to said first bit line and said second bit line, and outputting written data from one of said first function device and said second function device to said first and second bit lines, respectively, wherein
• said sense amplifier is connected to a first data bus that is connected to said first function device, and to a second data bus that is connected to said second function device,
• said write circuit is connected to the first data bus and to the second bus,
• when said memory cell is accessed from said first function device, the voltage read out from said memory cell is read out through said first bit line to the first data bus, and
• when said memory cell is accessed from said second function device, the voltage read out from said memory cell is read out through said second bit line to the second data bus and
• a memory access control unit which checks whether memory blocks accessed by said first and second function devices are the same, and permits simultaneous access by said first and second function devices to the memory blocks when the memory blocks accessed by said first and second function devices are not the same.