Embedded DRAM cache memory and method having reduced latency

An integrated circuit for use with a processor based system having a processor and a system memory, the integrated circuit comprising:

• a system memory controller structured to control the system memory of the processor based system;
• a processor interface coupled to the system memory controller, the processor interface structured to transmit information between the processor and the system memory;
• and
• a cache memory integrated with the system memory controller and the processor interface and coupled to the system memory controller and the processor interface, the cache memory comprising:
• a dynamic random access memory (“DRAM”) array;
• a tag memory;
• and
• a cache memory controller coupled to the DRAM array, the tag memory, the processor interface and the system memory controller, the cache memory controller being operable to receive a request for access to the cache memory, and, in response thereto to initiate an access the tag memory, to initiate an access to the DRAM array, and to initiate an access to the system memory, the cache memory controller being operable to initiate the access to the system memory before the cache memory controller receives a tag from the tag memory, the cache memory controller being further operable to couple data accessed from the system array to the processor responsive to the cache memory controller determining that the access to the cache memory will not result in a cache hit.

An integrated circuit for use with a processor based system having a memory requestor and a system memory, the integrated circuit comprising:

• a system memory controller structured to control the system memory of the processor based system;
• and
• a master scheduler integrated with the system memory controller and coupled to receive a data access request from the memory requester, the master scheduler being operable to generate a request for a cache memory access in response to receiving the data access request;
• a plurality of cache memories integrated with the memory controller and the master scheduler, the cache memories being coupled to the master scheduler, each of the cache memories comprising:
• a dynamic random access memory (“DRAM”) array;
• a tag memory;
• and
• a cache memory controller coupled to the master scheduler, the DRAM array, and the tag memory, the cache memory controller being operable to receive the request for cache memory access, and, in response thereto, to initiate an access to the tag memory and to initiate an access to the DRAM array, the cache memory controller initiating the access to the DRAM array before receiving a tag from the tag memory, the cache memory controller further being operable to determine based on the tag whether the access to the cache memory will result in a cache hit or a cache miss and, in response to determining that the access will result in a cache hit, to couple data from the DRAM array for coupling to the memory requester.

An integrated circuit for use with a processor based system having a memory requestor and a system memory, the integrated circuit comprising:

• a system memory controller structured to control the system memory of the processor based system;
• and
• a master scheduler integrated with the system memory controller and coupled to receive a data access request from the memory requester, the master scheduler being operable in response to receiving the data access request to generate a request for a cache memory access and to initiate an access to the system memory, the master scheduler initiating the access to the system memory before receiving a cache miss indication;
• a plurality of cache memories integrated with the system memory controller and the master scheduler, the cache memories being coupled to the master scheduler, each of the cache memories comprising:
• a dynamic random access memory (“DRAM”) array;
• a tag memory;
• and
• a cache memory controller coupled to the master scheduler, the DRAM array, and the tag memory, the cache memory controller being operable to receive the request for cache memory access, and, in response thereto, to initiate an access to the tag memory and to initiate an access to the DRAM array, the cache memory controller further being operable to determine based on the tag whether the access to the cache memory will result in a cache hit or a cache miss and, in response to determining that the access will result in a cache miss, to apply to the master scheduler the cache miss indication.

A computer system comprising:

• a processor;
• a system memory;
• an integrated circuit system controller coupled to the processor and to the system memory, the system controller comprising:
• a system memory controller coupled to the system memory, the system memory controller being structured to control the system memory;
• a processor interface coupled to the processor, the processor interface structured to transmit information between the processor and the system controller;
• and
• a cache memory coupled to the system memory controller and the processor interface, the cache memory comprising:
• a dynamic random access memory (“DRAM”) array;
• a tag memory;
• and
• a cache memory controller coupled to the DRAM array, the tag memory, the processor interface and the system memory controller, the cache memory controller being operable to receive a request for access to the cache memory, and, in response thereto, to initiate an access to the tag memory and to initiate an access to the DRAM array, the cache memory controller initiating the access to the DRAM array before receiving a tag from the tag memory, the cache memory controller further being operable to determine based on the tag whether the access to the cache memory will result in a cache hit and, in response to determining that the access will result in a cache hit, to couple data from the DRAM array to the processor, the cache memory controller further being operable to apply to the system memory controller a request for access to the system memory responsive to receiving the request for access to the cache memory and before the cache memory controller receives a tag from the tag memory, the cache memory controller being further operable to couple data accessed from the system memory to the processor responsive to the cache memory controller determining that the access to the cache memory will not result in a cache hit.

A computer system comprising:

• a processor;
• a system memory;
• an integrated circuit system controller coupled to the processor and to the system memory, the system controller comprising:
• a system memory controller coupled to the system memory, the system memory controller being structured to control the system memory;
• a processor interface coupled to the processor, the processor interface structured to transmit information between the processor and the system memory;
• and
• a cache memory integrated with the system memory controller and the processor interface and coupled to the system memory controller and the processor interface, the cache memory comprising:
• a dynamic random access memory (“DRAM”) array;
• a tag memory;
• and
• a cache memory controller coupled to the DRAM array, the tag memory, the processor interface and the system memory controller, the cache memory controller being operable to receive a request for access to the cache memory, and, in response thereto to initiate an access the tag memory, to initiate an access to the DRAM array, and to initiate an access to the system memory, the cache memory controller being operable to initiate the access to the system memory before the cache memory controller receives a tag from the tag memory, the cache memory controller being further operable to couple data accessed from the system array to the processor responsive to the cache memory controller determining that the access to the cache memory will not result in a cache hit.

In a computer system having a memory requester, a system controller coupled to the memory requester, and a system memory, the system controller comprising a system memory controller coupled to the system memory, and a cache memory coupled to the system memory controller and to the memory requester, the cache memory having a DRAM array, the system memory controller and the cache memory being fabricated as a common integrated circuit, a method of accessing data or instructions stored in the system memory and possibly also in the DRAM array of the cache memory, the method comprising:

• generating at the memory requester a request for access to the data or instructions;
• receiving at the cache memory the request for access to the data or instructions;
• initiating an access to the DRAM array before determining whether the access to the DRAM array will result in a cache hit or a cache miss;
• and
• applying to the system memory controller a request for access to the system memory responsive to receiving the request for access to the data or instructions and before determining whether the access to the DRAM array will result in a cache hit or a cache miss.

In a computer system having a memory requester, a system controller coupled to the memory requester, and a system memory, the system controller comprising a system memory controller coupled to the system memory, and a cache memory coupled to the system memory controller and to the memory requester, the cache memory having a DRAM array, the system memory controller and the cache memory being fabricated as a common integrated circuit, a method of accessing data or instructions stored in the system memory and possibly also in the DRAM array of the cache memory, the method comprising:

• generating at the memory requester a request for access to the data or instructions;
• receiving at the cache memory the request for access to the data or instructions;
• initiating an access to the DRAM array responsive to receiving the request for access to the data or instructions;
• and
• applying to the system memory controller a request for access to the system memory responsive to receiving the request for access to the data or instructions, the request for access to the system memory being applied to the system memory controller before determining whether the access to the DRAM array will result in a cache hit or a cache miss.