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US 6,789,168 B2Granted
Embedded DRAM cache
AssigneeMicron Technology, Inc.
InventorJoseph M. Jeddeloh
Life of this patent
Estimating the term…
Abstract
A large level three (L3) cache is integrated within the system chipset. The L3 cache is comprised of multiple embedded memory cache arrays. Each array is accessible independently of each other, providing parallel access to the L3 cache. By placing the L3 cache within the chipset, it is closer to the system processor with respect to the system memory. By using independent arrays, the L3 cache can handle numerous simultaneous requests. This reduces average memory latency and thus, increases system bandwidth and overall performance. By using embedded memory, the L3 cache can be implemented on the chipset and be much larger than the L1 and L2 caches without substantially increasing the size of the chipset and system.
Claims21
An integrated circuit for use with a processor system, said integrated circuit comprising:
- a memory controller for controlling a system memory of the processor system;
- a processor interface coupled to said memory controller, said processor interface for transmitting information between a processor and the system memory;
- a level three cache memory coupled to said memory controller and said processor interface, said level three cache memory comprising at least two independently accessible memory arrays that may be accessed independently and concurrently by the processor and other components of the system;
- and
- a master scheduler, said master scheduler processing requests for information from the processor and other components, forwarding information from said memory arrays to the processor and the other components, and resolving conflicts between said memory arrays.
2 more elements
An integrated circuit for use with a processor system, said integrated circuit comprising:
- a memory controller for controlling a system memory of the processor system;
- a processor interface coupled to said memory controller, said processor interface for transmitting information between a processor and the system memory, the processor communicating with level one and level two cache memories;
- and
- a level three cache memory coupled to said memory controller and said processor interface, said level three cache memory comprising at least two independently accessible memory arrays connected to a respective local memory controller and tag array that may be accessed independently and concurrently by the processor and other components of the system.
1 more element
A north bridge integrated circuit comprising:
- a level three cache memory integrated with and coupled to at least memory controller and a processor interface, said level three cache memory comprising at least one embedded dynamic random access memory array that may be accessed by multiple requesting devices independently and concurrently;
- and
- a master scheduler, said master scheduler processing requests for information from a processor and other components, forwarding information from said at least one embedded dynamic random access memory array to the processor and the other components, and resolving conflicts between said embedded dynamic random access memory arrays.
A north bridge integrated circuit comprising:
- a level three cache memory integrated with and coupled to at least a memory controller and a processor interface, said level three cache memory comprising at least one embedded dynamic random access memory array that may be accessed by multiple requesting devices independently and concurrently, wherein each of said at least one array is connected to a respective local memory controller and tag array.
A processor system comprising:
- a processor;
- a system memory device;
- and
- a north bridge coupled to said processor and said system memory device, said north bridge comprising:
- a memory controller for controlling said system memory device;
- a processor interface coupled to said memory controller, said processor interface for transmitting information between said processor and said system memory device;
- and
- a cache memory coupled to said memory controller and said processor interface, said cache memory comprising at least two independently accessible memory arrays that may be accessed independently and concurrently by the processor and other components of the system;
- and
- a master scheduler, said master scheduler processing requests for information from said processor and other components, forwarding information from said memory arrays to said processor and the other components, and resolving conflicts between said memory arrays.
7 more elements
A processor system comprising:
- a processor;
- a system memory device;
- and
- a north bridge coupled to said processor and said system memory device, said north bridge comprising:
- a memory controller for controlling said system memory device;
- a processor interface coupled to said memory controller, said processor interface for transmitting information between said processor and said system memory device;
- and
- a cache memory coupled to said memory controller and said processor interface, said cache memory comprising at least two independently accessible memory arrays, wherein each memory array of said cache memory is connected to a respective local memory controller and tag array that may be accessed independently and concurrently by the processor and other components of the system.
5 more elements
A processor system comprising:
- a processor, said processor including level one and level two cache memories;
- a system memory device;
- and
- a north bridge integrated circuit coupled to said processor and said system memory device, said north bridge integrated circuit comprising:
- a level three cache memory integrated with and coupled to at least memory controller and a processor interface, said level three cache memory comprising at least one embedded dynamic random access memory embedded dynamic random access memory array that may be accessed by multiple requesting devices independently and concurrently;
- and
- a master scheduler, said master scheduler processing requests for information from said processor and other components of the system, forwarding information from said embedded dynamic random access memory arrays to said processor and the other components, and resolving conflicts between said embedded dynamic random access memory arrays.
4 more elements
A processor system comprising:
- a processor, said processor including level one and level two cache memories;
- a system memory device;
- and
- a north bridge integrated circuit coupled to said processor and said system memory device, said north bridge integrated circuit comprising:
- a level three cache memory integrated with and coupled to at least memory controller and a processor interface, said level three cache memory comprising at least one embedded dynamic random access memory array that may be accessed by multiple requesting devices independently and concurrently, wherein each of said at least one eDRAM array is connected to a respective local memory controller and tag array.
2 more elements
A processor system comprising:
- a processor;
- a system memory device;
- and
- a north bridge coupled to said processor and said system memory device, said north bridge comprising:
- a switch;
- a graphics interface connected to said switch;
- a peripheral component interchange bus interface connected to said switch;
- a memory controller connected to said switch, said memory controller controlling said system memory device;
- a processor interface connected to said switch;
- and
- a cache memory coupled to said memory controller and said processor interface, said cache memory comprising a plurality of independently and concurrently accessible embedded dynamic random access memory arrays, each embedded dynamic random access memory array being connected to a respective local memory controller and tag array and being configured as a direct mapped cache.
8 more elements
Dependencies are inferred from the claim text.