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US 6,789,155 B2Granted
System and method for controlling multi-bank embedded DRAM
AssigneeMicron Technology, Inc.
InventorJoseph Jeddeloh
Life of this patent
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Abstract
In a computer or microprocessor-based system having a plurality of resources making memory requests of a plurality of banks of memory, a switch-based interconnect system allows multiple simultaneous connections between resources and memory banks, maximizing memory throughput and bandwidth concurrency. The invention is particularly useful in devices having embedded banks of memory, where there are no external constraints requiring use of a bus architecture, but can be used with discrete devices as well.
Claims102
A memory control system comprising:
- a plurality of banks of memory;
- a plurality of system resources that submit memory requests to said memory;
- and
- a switch interconnecting said plurality of banks of memory and said plurality of system resources and establishing communications between (a) a respective one of said resources, and (b) a respective one of said banks of memory of which said respective one of said resources makes a request, when said respective one of said resources and said respective one of said banks of memory are both available, wherein:
- said switch comprises:
- a plurality of memory ports at least corresponding to said plurality of banks of memory, each of said banks of memory being connected to one of said memory ports, and
- a plurality of requestor ports at least corresponding to said plurality of system resources, each of said at least one system resource being connected to one of said at least one requestor ports;
- each one of at least some of said banks of memory signals to said switch (a) when said one of at least some of said banks of memory is busy and unavailable to accept requests, (b) when said one of at least some of said banks of memory is available to accept requests, and (c) when said one of at least some of said banks of memory has data to return in response to a request;
- said switch forwards a request from a requesting one of said resources to a destination one of said banks of memory when said destination one of said banks of memory signals its availability to receive requests;
- each one of at least some of said system resources signals to said switch (a) when said one of at least some of said system resources is busy and unavailable to accept data, and (b) when said one of at least some of said system resources is available to accept data;
- and
- said switch establishes a connection between a requesting one of said resources and a destination one of said embedded banks of memory when said destination one of said embedded banks of memory signals that it has data to return and said requesting one of said resources signals that it is available to receive data.
9 more elements
A memory control system comprising:
- a plurality of banks of memory means;
- a plurality of system resource means that submit memory requests to said memory means;
- and
- switch means interconnecting said plurality of banks of memory means and said plurality of system resource means and establishing communications between (a) a respective one of said resource means, and (b) a respective one of said banks of memory means of which said respective one of said resource means makes a request, when said respective one of said resource means and said respective one of said banks of memory means are both available;
- wherein:
- said switch means comprises:
- a plurality of memory port means at least corresponding to said plurality of embedded banks of memory means, each of said embedded banks of memory means being connected to one of said memory port means, and
- a plurality of requestor port means at least corresponding to said plurality of system resource means, each of said at least one system resource means being connected to one of said at least one requestor port means;
- each one of at least some of said embedded banks of memory means signals to said switch means (a) when said one of at least some of said embedded banks of memory means is busy and unavailable to accept requests, (b) when said one of at least some of said embedded banks of memory means is available to accept requests, and (c) when said one of at least some of said embedded banks of memory means has data to return in response to a request;
- and
- said switch means forwards a request from a requesting one of said resources to a destination one of said embedded banks of memory means when said destination one of said embedded banks of memory means signals its availability to receive requests;
- each one of at least some of said system resource means signals to said switch means (a) when said one of at least some of said system resource means is busy and unavailable to accept data, and (b) when said one of at least some of said system resource means is available to accept data;
- and
- said switch means establishes a connection between a requesting one of said resource means and a destination one of said embedded banks of memory means when said destination one of said embedded banks of memory means signals that it has data to return and said requesting one of said resource means signals that it is available to receive data.
11 more elements
A memory control method for use in a system having:
- a plurality of banks of memory, and
- a plurality of system resources that submit memory requests to said memory;
- said method comprising:
- establishing communications between (a) a respective one of said resources, and (b) a respective one of said banks of memory of which said respective one of said resources makes a request, when said respective one of said resources and said respective one of said banks of memory are both available:
- wherein said establishing comprises:
- each one of at least some of said banks of memory signalling (a) when said one of at least some of said banks of memory is busy and unavailable to accept requests, (b) when said one of at least some of said banks of memory is available to accept requests, and (c) when said one of at least some of said banks of memory has data to return in response to a request;
- forwarding a request from a requesting one of said resources to a destination one of said banks of memory when said destination one of said banks of memory signals its availability to receive requests;
- each one of at least some of said system resources signalling (a) when said one of at least some of said system resources is busy and unavailable to accept data, and (b) when said one of at least some of said system resources is available to accept data;
- and
- establishing a connection between a requesting one of said resources and a destination one of said banks of memory when said destination one of said banks of memory signals that it has data to return and said requesting one of said resources signals that it is available to receive data.
7 more elements
Dependencies are inferred from the claim text.