Bridge for coupling digital signal processor to on-chip bus as slave
AssigneeLSI Logic Corporation
InventorCharles H. Stewart
Life of this patent
Estimating the term…
Abstract
A bridge for connecting a DSP to an ASIC on-chip bus as a slave. The bridge couples signals between a DSP internal memory direct memory interface and an on-chip bus such as the AMBA AHB. The bridge includes a generic slave module which provides direct connections to the on-chip bus in the on-chip bus protocol. It also includes a slave engine connected to the DSP memory interface to control read and write transactions with the memory. The generic slave and the slave engine are coupled by a pulse grower and pulse shaver to allow the engine to operate at DSP clock frequency while the generic slave operates at the usually slower on-chip bus frequency. The bridge allows masters in the ASIC to perform read and write transactions with the DSP internal memory.
Claims27
Apparatus for connecting a digital signal processor to an application specific integrated circuit (ASIC) on-chip bus as a slave comprising:
- a bridge for coupling signals between internal memory of a digital signal processor and an ASIC on-chip bus, said bridge comprising:
- a generic bus slave coupled to said ASIC on-chip bus, said generic bus slave translating on-chip bus protocol signals into bridge bus protocol signals;
- a slave engine coupled to said digital signal processor, said slave engine having control logic for providing signals which control the flow of instructions and data to and from said internal memory of said digital signal processor;
- a grower module coupled between said slave engine and said generic bus slave, said grower module lengthening bridge bus protocol signals being transmitted from said slave engine to said generic bus slave;
- and
- a shaver module coupled between said slave engine and said generic bus slave, said shaver module shortening bridge bus protocol signals being transmitted from said generic bus slave to said slave engine;
- wherein said digital signal processor and said slave engine operate at a first clock frequency;
- and
- wherein said on-chip bus and said generic bus slave operate at a second clock frequency different than said first clock frequency.
A method for executing read and write requests initiated on an application specific integrated circuit (ASIC) on-chip bus in internal memory of a digital signal processor coupled to said ASIC on-chip bus by a bridge, comprising:
- converting read and write requests from an on-chip bus protocol to a bridge bus protocol;
- coupling said converted bus bridge protocol signals to said internal memory of said digital signal processor;
- reducing the length of said converted bus bridge protocol signals while coupling said converted bus bridge protocol signals to said internal memory of said digital signal processor;
- coupling bus bridge protocol signals from said internal memory of said digital signal processor to said ASIC on-chip bus;
- and
- while coupling said bus bridge protocol signals from said internal memory of said digital signal processor to said ASIC on-chip bus, increasing the length of said bus bridge protocol signals from said internal memory of said digital signal processor and converting said increased length bus bridge protocol signals from said bus bridge protocol to the on-chip bus protocol;
- wherein said on-chip bus and a first portion of said bridge which converts signals between the on-chip bus Protocol and the bus bridge protocol bus operate at a first clock frequency and wherein said digital signal processor and a second portion of said bridge which couples said digital signal processor to said first portion of said bridge operate at a second clock frequency different than said first clock frequency.
Apparatus for executing read and write requests initiated on an application specific integrated circuit (ASIC) on-chip bus in internal memory of a digital signal processor comprising:
- bridge means for coupling signals between internal memory of a digital signal processor and an ASIC on-chip bus, said bridge means comprising:
- generic slave means for converting read and write requests from an on-chip bus protocol to a bridge bus protocol;
- engine means for converting said read and write requests in said bridge bus protocol to control signals causing read and write transactions with said internal memory of said digital signal processor;
- wherein said digital signal processor and said engine means operate at a first clock frequency and said ASIC on-chip bus and said generic slave means operate at a second clock frequency different than said first clock frequency.
Dependencies are inferred from the claim text.