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AssigneeSeiko Epson Corporation
InventorMotoki Yoshizawa
Estimating the term…
Firmware has a plurality of interface modules for mutually transferring signals between a CPU (11) and a plurality of mutually different interface units (40, 41), the type of controller (40a, 41a) is identified by an identifying module, and the CPU (11) is operated by using one of the interface modules corresponding to the controller (40a, 41a). Since the assignment of the controllers (40a, 41a) in memory space of the CPU (11) is different in accordance with the types of the interface units (40, 41), the type of the interface unit (40, 41) can be identified by a return value at a time when data is written in a certain region of the memory space, so that the CPU (11) can be operated in accordance with the type of the interface unit (40, 41).
A computer peripheral apparatus, comprising:
A computer readable medium having a program stored thereon for controlling a computer peripheral apparatus which includes a central processing unit and a plurality of interface units of different types including controllers which control data transfer between a computer and the central processing unit, the program comprising the steps of:
A computer readable medium having a program stored thereon for controlling a computer peripheral apparatus which includes a central processing unit, a plurality of interface units of different types including controllers which control data transfer between a computer and the central processing unit, a plurality of controlling devices, and an identifying device, the program causes one of the plurality of controlling devices to mutually transfer a signal between the central processing unit and one of the plurality of interface units, the program, causes the identifying device to identify a type of one of the controllers by a valid return value and operate the central processing unit by using one of the plurality of controlling devices that corresponds to the one of the controllers, the return value for each region in a memory space of the central processing unit is determined to be valid when the central processing unit writes data at an address located in the region of the memory space, the address coincides with one of the addresses assigned to separate registers located in the controller of a connected one of the plurality of interface units, and the controllers of the plurality of interface units are assigned to respective ones of the regions, in the memory space of the central processing unit, which are mutually different.
Dependencies are inferred from the claim text.