Semiconductor memory device allowing reduction of I/O terminals
AssigneeRenesas Technology Corp.
InventorTakashi Itoh
Life of this patent
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Abstract
A semiconductor memory device includes an address buffer, a clock buffer, a control signal buffer, a control circuit, a mode register, a memory cell array, a signal select circuit, a DLL, an I/O buffer and a QS buffer. The mode register provides a signal at H- or L-level to the signal select circuit. The signal select circuit selects a data strobe signal sent from an I/O terminal in accordance with the signal at L-level, and provides it to the QS buffer. The signal select circuit selects a clock sent from an I/O terminal in accordance with the signal at H-level, and provides it to the QS buffer.
Claims16
A semiconductor memory device for operating selectively in a normal operation mode for periodically performing writing and reading of data, and in a slow operation mode for periodically performing writing and reading of said data at a lower speed than that in said normal operation mode, comprising:
- a plurality of memory cells for storing the data;
- a signal select circuit for selecting either a first signal received from an I/O terminal used only in said normal operation mode or a second signal received from an I/O terminal used in both of said slow and normal operation modes;
- and
- a peripheral circuit for performing the writing and/or reading of said data into and/or from said plurality of memory cells in said slow operation mode by using said second signal when said signal select circuit selects said second signal, and performing the writing and/or reading of said data into and/or from said plurality of memory cells in said normal operation mode by using said first signal when said signal select circuit selects said first signal, wherein
- said signal select circuit selects said first signal in said normal operation mode, and selects said second signal in said slow operation mode.
Dependencies are inferred from the claim text.