Efficient method to obtain device addresses from devices on a bus
AssigneeIntel Corporation
InventorRobert A. Dunstan
Life of this patent
Estimating the term…
Abstract
A requesting device sends a request, intended to read one or more device addresses on a line of a bus. One or more sets of commands are then sent by the requesting device, where each set of commands is intended to read one device address. If, while a first device is writing its device address, the line fails to display any of the driven bit values of the first address, because the second device is simultaneously writing a second address on the line in response to the request, then the first device stops writing the first address. The first device does not write the first address again until after the second device has finished writing the second address. The first and second addresses uniquely identify the first and second devices.
Claims21
A method for obtaining device addresses over a line of a bus, comprising:
- sending a request, intended to read one or more device addresses, on the line, and then sending one or more sets of commands on the line, each set of commands being intended to read one device address;
- attempting to write a first address on the line in response to the request, by a first device driving one or more of a plurality of first bit values, which define the first address, on the line in response to a first set of commands, respectively;
- and
- if, while writing the first address, the line fails to display any one of the driven plurality of first bit values, because a second device is simultaneously writing a second address on the line in response to the request, then the first device stops writing the first address and does not write the first address again until after the second device has finished writing the second address, the first and second addresses uniquely identifying the first and second devices.
A device to communicate over a bus line, comprising:
- an active switching circuit to drive the line by subjecting the line to one of a high voltage, a low voltage, and a high impedance, in response to an input;
- a receiver circuit to translate a signal on the line into one of two logic states at an output;
- and
- control logic coupled to the input of the active switching circuit to forward a request intended to read device addresses on the line, and then send a plurality of sets of commands on the line, each set of commands being intended to read one device address,
- the control logic being further coupled to the output of the receiver circuit to read one bit value of a device address after sending each command in a set,
- the device to return a list, where the list includes one or more device addresses that were read on the line following the request, after reading on the line a last device address whose bit values are all equal to a predetermined stop value.
A device to communicate over a bus line, comprising:
- an active switching circuit to drive the line by subjecting the line to one of a high voltage, a low voltage, and a high impedance, in response to an input;
- a receiver circuit to translate a signal on the line into one of two logic states at an output;
- and
- control logic coupled to the output of the receiver circuit to receive (1) a request intended to read device addresses on the line, and (2) one or more sets of commands, each set of commands being intended to read one device address,
- the control logic being further coupled to the input of the active switching circuit to attempt to write a device address on the line in response to the request, by causing the active switching circuit to drive a plurality of bit values, which define the device address, on the line in response to a first one of the one or more sets of commands, and
- if, while writing the device address, the control logic fails to read back any one of the driven plurality of bit values, then the control logic loses arbitration, stops writing the device address and does not attempt to write the device address again until a second one of the one or more sets of commands is received.
The device of 13 wherein the control logic is to detect each command when the receiver circuit detects a low to high voltage transition at the beginning of a bit time, and then causes the active switching circuit to present a high impedance to the line at a predetermined time after the beginning of the bit time.
A computer system comprising:
- a printed wiring board (PWB);
- a serial bus having only one line, formed in the PWB;
- a system battery module connected to the line;
- a second device connected to the line;
- and
- a host device connected to the line to send a request, intended to read one or more device addresses, on the line, and then send one or more sets of commands on the bus, each set of commands being intended to read one device address, and wherein
- if the system battery module attempts to write a first device address on the line in response to the request, by driving one or more of a plurality of first bit values, which define the first device address, on the line in response to a first set of commands, respectively, and if, while writing the first address, the line fails to display any one of the driven plurality of first bit values, because the second device in the system is simultaneously writing a second address on the line in response to the request, then the system battery module stops writing the first device address and does not write the first device address again until after the second device has finished writing the second address, the first and second addresses uniquely identifying the system battery module and the second device.
Dependencies are inferred from the claim text.