Sense-amp based adder with source follower evaluation tree
AssigneeInternational Business Machines Corporation
InventorsJae-Joon Kim, Ching-Te K. Chuang, Rajiv V. Joshi, Kaushik Roy
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Abstract
A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.
Claims6
An N-bit two level lookahead adder for adding two N-bit numbers, comprising summing means for calculating alternative partial M-bit sums;
- a first set of carry modules for generating gi, pi and ki signals for each of the N bits;
- a second set of carry modules, responsive to said gi, pi and ki signals, for generating a set of M-bit G, P and K signals therefrom, each of said set of carry modules having a sense amplifier connected to a logic evaluation module containing two connecting nodes connected to said sense amplifier, and a chain of source follower transistors having a first node, a final node and a set of intermediate nodes controllably connected to both said two connecting nodes by first and second sets of connecting transistors,
- first precharge means for precharging each of said set of two connecting nodes to ground;
- means for charging said first node to a reference voltage other than ground in an evaluation mode;
- and
- a set of output modules, responsive to said set of carry signals, for selecting alternative partial sums and connecting a selected set of said alternative partial sums to a set of output terminals.
Dependencies are inferred from the claim text.