Real-time method for bit-reversal of large size arrays
AssigneeTropic Networks Inc.
InventorDongxing Jin
Life of this patent
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Abstract
A digital signal processor DSP for bit-reversal of a large data array of a size has a direct memory access (DMA) controller for performing in-place bit reversal routines on an external memory during a first stage, and a central processing unit (CPU) for swapping small sub-arrays on internal memory in a second stage. The two stage method according to the invention importantly reduces the real-time implementation for sorting large size data arrays on uni-processor DSP platforms, by extensively using the external memory and avoiding a random access to the internal memory. As well, the invention provides for improved dense integration and reduced costs when used in dense wavelength division multiplexing (DWDM) systems.
Claims17
A method for bit reversal of large data array on a uni-processor platform, comprising:
- determining the ratio K between the size M×2M of said large data array stored in an external memory, and the size M×2Q of a small array, available on an internal memory, such that K+Q=M;
- performing an in-place bit reversal operation for K bits of said large data array on said external memory;
- and
- performing a bit reversal operation for the remaining Q bits of said large data array on said small array of said internal memory.
A digital signal processor DSP for bit-reversal of a large data array of a size M×2M of bits, comprising:
- an internal memory for storing a small array of a size M×2Q;
- a direct memory access (DMA) controller for performing a bit reversal operation on an external memory;
- a central processing unit (CPU) for performing a bit reversal operation on said small array;
- and
- a bus between said internal memory, said CPU and said DMA for allowing bit transfer between said external and internal memories under control of said DMA controller during a first stage of said bit-reversal operation, and for allowing bit transfer between said internal memory and said external memory under control of said CPU during a second stage of said bit reversal operation.
Dependencies are inferred from the claim text.