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US 6,789,056 B2Granted
DSP interface for packet processing
AssigneeIntel Corporation
InventorsBapi Vinnakota, Sameer Nanavati, Saurin Shah, Nicholas E. Duresky
Life of this patent
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Abstract
A method, apparatus, and system for communicating between a digital signal processor (DSP) and a packet processor.
Claims25
An apparatus, comprising:
- a packet processing engine;
- a packet processor memory;
- and
- a digital signal processor interface to exchange packets with a plurality of digital signal processors, the digital signal processor including:
- an interface memory;
- a first component adapted to obtain a packet of data from a digital signal processor, assign a priority to the packet of data, and to place the packet of data in one of a first plurality of queues stored at the digital signal processor interface based, at least in part, on the priority;
- and
- a second component adapted to provide the packet of data either (i) to one of a second plurality of queues stored at the packet processor memory or (ii) to the packet processing engine based, at least in part, on the priority.
5 more elements
An apparatus, comprising:
- a packet processing engine;
- a packet processor memory;
- and
- a digital signal processor interface to exchange packets with a plurality of digital signal processors, the digital signal processor including:
- an interface memory;
- a first component adapted to obtain a packet of data from a digital signal processor, assign a priority to the packet of data, and to place the packet of data in one of a first plurality of queues stored at the digital signal processor interface based, at least in part, on the priority;
- and
- a second component in the adapted to place the packet of data into one of a second plurality of queues stored at the packet processor memory based, at least in part, on the one of the first plurality of queues, and to notify the packet processing engine of an availability of the packet of data in the one of the second plurality of queues.
5 more elements
A method, comprising:
- determining that a first digital signal processor has a first packet of data available;
- obtaining the first packet of data from the first digital signal processor;
- determining a priority for the first packet of data;
- providing the first packet of data to memory of a packet processor based, at least in part, on the priority;
- providing a notification that the first packet of data is available for processing;
- receiving a notification that a second packet of data is available in the packet processor;
- determining a channel and a second digital signal processor associated with the second packet of data;
- and
- providing the second packet of data to the channel in the second digital signal processor.
6 more elements
A medium storing instructions adapted to be executed by a processor to perform a method of facilitating data transfer, the method comprising:
- determining that a first digital signal processor has a first packet of data available;
- obtaining the first packet of data from the first digital signal processor;
- determining a priority for the first packet of data;
- providing the first packet of data to memory of a packet processor based, at least in part, on the priority;
- providing a notification that the first packet of data is available for processing;
- receiving a notification that a second packet of data is available in the packet processor;
- determining a channel and a second digital signal processor associated with the second packet of data;
- and
- providing the second packet of data to the channel in the second digital signal processor.
6 more elements
An apparatus, comprising:
- a first component in a packet processor adapted to (i) determine that a first digital signal processor has a first packet of data available, (ii) obtain the first packet of data from the first digital signal processor, and (iii) determine a priority for the first packet of data;
- and
- a second component to (i) provide the first packet of data to memory of a packet processor based, at least in part, on the priority, (ii) provide a notification that the first packet of data is available for processing, and (iii) receive a notification that a second packet of data is available in the packet processor;
- wherein the first component is to further (i) determine a channel and a second digital signal processor associated with the second packet of data, and (ii) provide the second packet of data to the channel in the second digital signal processor.
1 more element
A system comprising:
- a packet processor including a digital signal processor interface;
- a plurality of digital signal processors in communication with the digital signal processor interface;
- and
- a modem connectable to one of the digital signal processors,
- wherein the digital signal processor interface includes:
- a first component adapted to (i) determine that a first digital signal processor has a first packet of data available, (ii) obtain the first packet of data from the first digital signal processor, and (iii) determine a priority for the first packet of data;
- and
- a second component to (i) provide the first packet of data to memory of a packet processor based, at least in part, on the priority, (ii) provide a notification that the first packet of data is available for processing, and (iii) receive a notification that a second packet of data is available in the packet processor,
- wherein the first component is to further (i) determine a channel and a second digital signal processor associated with the second packet of data, and (ii) provide the second packet of data to the channel in the second digital signal processor.
6 more elements
Dependencies are inferred from the claim text.