Output buffer type asynchronous transfer mode switch

An output buffer type asynchronous transfer mode switch comprising;

• a plurality of input ports into which cells from input circuits are inputted,
• a first multiplexer for multiplexing cells inputted through said plurality of input ports,
• a plurality of output ports for sending out cells to output circuits,
• a plurality of filters which are provided correspondingly to said output ports and make only the cells addressed to the corresponding output ports out of cells multiplexed by said first multiplexer pass through them, and
• a plurality of output buffers for temporarily storing in them the cells which have passed through said plurality of filters, wherein;
• at least one input port out of said plurality of input ports and at least one output port out of said plurality of output ports are respectively a high-speed input port and a high-speed output port each having a transmission rate being 2 or larger integer times higher than the other input and output ports, respectively, and
• said asynchronous transfer mode switch comprises;
• numbering parts which are provided correspondingly to said plurality of input ports and add a sequence number indicating the order in which said cell has been inputted for its logical connection number to a cell inputted from each of said plural input ports,
• a demultiplexer for separating cells which are inputted through said high-speed input port and each are given a number by said numbering part to a plurality of paths so that said cells become equal in transmission rate to cells inputted through the other input ports than said high-speed input port,
• a second multiplexer for multiplexing and outputting cells outputted from a plurality of output buffers corresponding to said high-speed output port out of said plurality of output buffers at the transmission rate of said high-speed output port, and
• order restoring parts which are provided correspondingly to said plurality of output ports and which, on the basis of said sequence numbers added to the cells multiplexed and outputted by said second multiplexer and the cells outputted from the other output buffers than the output buffers corresponding to said high-speed output port, correct the order of outputting said cells and output them, and wherein;
• said first multiplexer multiplexes the cells inputted through the other input ports than said high-speed input port and the cells separated by said demultiplexer.