Semiconductor memory device
AssigneeHitachi, Ltd.
InventorYasuhiko Takahashi
Life of this patent
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Abstract
To provide a semiconductor memory device which has high speed operation and multifunctionality, and is suitable for 3D imaging. Data is output to a data terminal in synchronism with a synchronization signal during data read, write data is input via the data terminal in synchronism with a synchronization signal during data write, input of write data via the data terminal is permitted via the data terminal in a first period wherein output of read data to the data terminal should be performed, a second period is provided from when a write specification is issued to when input of write data starts, and a third period is provided during which input of write data is performed.
Claims14
A semiconductor memory device wherein data read operations and write operations are specified by commands, and which can respond to:
- a first read command which performs data readout from a memory address according to address information;
- and
- a second read command which has a different command code from the first command, and performs data readout from a memory address sequentially removed from a read start address.
A semiconductor memory device whereof the internal operation is specified by an operating specification command from outside, which can respond to:
- a first command having a first command code, which clears the contents of a plurality of memory cells which form a memory block whereof a period is a first unit period determined by the synchronization signal, and
- a second command having a different code from the first command code, which writes data from a data transfer region to an addressed memory cell in a memory block whereof a period is a second unit period determined by the synchronization signal.
Dependencies are inferred from the claim text.