System and method for low area self-timing in memory devices

A method for self-timing synchronization for a row of memory banks in a memory device, comprising the operations of:

• providing a dummy global wordline signal to at least two memory banks, each memory bank including a model row in electrical communication with the dummy global wordline signal, each model row comprising a plurality of load cells;
• providing a self-timing reset signal for the memory device using a single global timing column in electrical communication with the dummy global wordline signal, wherein the global timing column comprising a plurality of load cells;
• and
• resetting each active memory bank in the row of memory banks using the self-timing reset signal.

A memory device having a self-timing system for each row of memory banks, comprising:

• a plurality of global wordlines drivers providing a plurality of global wordline signals to a row of memory banks, each global wordline signal configured to follow a global timing signal when the particular global wordline is selected;
• and
• a dummy global wordline signal configured to follow a global timing pulse,
• wherein the row of memory banks includes at least two non-timing memory banks, each non-timing memory bank including a model row in electrical communication with the dummy global wordline signal, each model row comprising a plurality of load cells, and wherein the row of memory banks further includes a timing memory bank having a global timing column comprising a plurality of load cells coupled via at least one bit line, the global timing column responding to the dummy global wordline signal to provide a self-timing reset signal for the memory device, wherein the self-timing reset signal is provided to each active memory bank in the row of memory banks.