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US 6,788,614 B2Granted
Semiconductor memory with wordline timing
AssigneeMicron Technology, Inc.
InventorRamandeep S. Sawhney
Life of this patent
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Abstract
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.
Claims27
A timing circuit, comprising:
- a first input adapted to receive at least one first input signal, the first input signal including a sense amplifier isolation signal;
- adapted to isolate a first memory array;
- a second input adapted to receive at least one second input signal, the second input signal including a sense amplifier isolation signal adapted to isolate a second memory array;
- a first output connected to a first address decoder, adapted to address the second memory array;
- a second output connected to a second address decoder adapted to address the first memory array;
- and
- wherein the timing circuit is adapted to selectively activate the second address decoder based on the second input signal and the first address decoder based on the first input signal.
4 more elements
A timing circuit, comprising:
- a first input adapted to receive at least one first input signal, the first input signal including a first sense amplifier isolation signal;
- a second input adapted to receive at least one second input signal, the second input signal including a sense amplifier isolation signal;
- a first output connected to a first address decoder;
- a second output connected to a second address decoder;
- wherein the timing circuit is adapted to selectively activate the second address decoder based on the second input signal and the first address decoder based on the first input signal;
- and
- wherein the second isolation signal is associated to a first memory array separate from a second memory array, wherein the first isolation signal is associated to the second memory array.
4 more elements
A timing circuit connected to a first wordline decoder of a first memory array, and a second wordline decoder of a second memory array, the timing circuit comprising:
- a first input adapted to receive at least one first input signal, the first input signal including a sense an isolation signal connected to a sense amplifier for the second memory array;
- a first input adapted to receive at least one first input signal, the first input signal including a sense amplifier isolated signal connected to a sense amplifier for the second memory array;
- a first output connected to the first wordline decoder, wherein the timing circuit is adapted to activate the first wordline decoder based on the first input signal;
- a second input adapter to receive at least one second input signal, the second input signal including a sense amplifier isolated signal connected to a sense amplifier for the first memory array;
- and
- a second output connected to the second wordline decoder, wherein the timing circuit is adapted to activate the second wordline decoder based on the second input signal.
3 more elements
An integrated circuit, comprising:
- a memory array,
- a plurality of sense amplifiers operably connected to the memory array,
- an isolation gaze system operably connected between the memory array and the sense amplifiers,
- a first timing circuit operably connected to the isolation gate system comprising:
- a first input adapted to receive at least one first input signal, the first input signal including a first sense amplifier isolation signal;
- a first output operably connected to an address decoder and the first input, wherein the first timing circuit activates the address decoder for a first sub-array of the memory array based on the first input signal;
- and
- a second timing circuit operably connected to the isolation gate system, comprising:
- a second input adapted to receive at least one second input signal, the second input signal including a second sense amplifier isolation signal;
- and
- a second output operably connected to an address decoder and the second input wherein the second timing circuit activates the address decoder for a second sub-array of the memory array based on the second input signal.
8 more elements
Dependencies are inferred from the claim text.