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US 6,788,613 B1Granted
Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
AssigneeMicron Technology, Inc.
InventorsAlistair Gratrex, Graham Kirsch
Life of this patent
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Abstract
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.
Claims50
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed, the memory array comprising:
- a memory array having (r·s·t) memory locations, the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array, both m and n being multiples of r and the sum of (m/r) and (n/r) equal to s, the memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.
A multi-port memory having a common memory interface and a plurality of memory ports through which the multi-port memory is accessed, the multi-port memory comprising:
- a memory array having (r·s·t) memory locations, the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array, both m and n being multiples of r and the sum of m and n equal to s, the memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array, the (r×s×t) memory array organized as s (r×t) memory segments, each memory segment having a set of t input/output terminals through which the memory locations of the respective memory segment are accessed;
- and
- a multiplexer coupled to the s sets of t input/output terminals of the s (r×t) memory segments, the multiplexer selecting one of the s sets of t input/output terminals for coupling to the common memory interface for access to the (r×s×t) memory array.
A multi-port memory having a common data interface and a plurality of memory ports, the multi-port memory comprising:
- a first memory array having (m·n) memory locations and having a first set of n input/output terminals coupled to a first of the plurality of memory ports for providing access to the first memory array organized as a (m×n) memory array, m being a multiple of a value r;
- a second memory array having (q·n) memory locations and having a first set of n input/output terminals coupled to a second of the plurality of memory ports for providing access to the second memory array organized as a (q×n) memory array, q being a multiple of the value r, the first and second memory arrays each segmented into at least one memory segment organized as a (r×n) memory segment, each memory segment of the first and second memory arrays having a respective set of n input/output terminals through which the (r·n) memory locations of the respective memory segment are accessed;
- and
- a multiplexer coupled to the sets of n input/output terminals of each memory segment of the first and second memory arrays, the multiplexer selecting one of the sets of n input/output terminals for coupling to the common data interface for providing access to the first and second memory arrays organized as a (r×((m/r)+(q/r))×n) memory array.
1 more element
A processing system, comprising:
- a common address and data bus;
- a plurality of sets of address and data busses;
- a memory coupled to the common address and data bus;
- first logic circuitry coupled to a first set of the plurality of sets of address and data busses;
- second logic circuitry coupled to a second set of the plurality of sets of address and data busses;
- and
- a multi-port memory having a common memory interface coupled to the common address and data busses through which data can be transferred between the memory and the multi-port memory, and a plurality of memory ports coupled to a respective set of address and data busses through which the first and second logic circuitry can access the multi-port memory, the multi-port memory comprising:
- a memory array having (r·s·t) memory locations, the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array, both m and n being multiples of r and the sum of m and n equal to s, the memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array, the (r×s×t) memory array organized as s (r×t) memory segments, each memory segment having a set of t input/output terminals through which the memory locations of the respective memory segment are accessed;
- and
- a multiplexer coupled to the s sets of t input/output terminals of the s (r×t) memory segments, the multiplexer selecting one of the s sets of t input/output terminals for coupling to the common memory interface for access to the (r×s×t) memory array.
7 more elements
A processing system, comprising:
- a common address and data bus;
- a plurality of sets of address and data busses;
- a memory coupled to the common address and data bus;
- first logic circuitry coupled to a first set of the plurality of sets of address and data busses;
- second logic circuitry coupled to a second set of the plurality of sets of address and data busses;
- and
- a multi-port memory having a common memory interface coupled to the common address and data busses through which data can be transferred between the memory and the multi-port memory, and a plurality of memory ports coupled to a respective set of address and data busses through which the first and second logic circuitry can access the multi-port memory, the multi-port memory comprising:
- a first memory array having (m·n) memory locations and having a first set of n input/output terminals coupled to a first of the plurality of memory ports for providing access to the first memory array organized as a (m×n) memory array, m being a multiple of a value r;
- a second memory array having (q·n) memory locations and having a first set of n input/output terminals coupled to a second of the plurality of memory ports for providing access to the second memory array organized as a (q×n) memory array, q being a multiple of the value r, the first and second memory arrays each segmented into at least one memory segment organized as a (r×n) memory segment, each memory segment of the first and second memory arrays having a respective set of n input/output terminals through which the (r·n) memory locations of the respective memory segment are accessed;
- and
- a multiplexer coupled to the sets of n input/output terminals of each memory segment of the first and second memory arrays, the multiplexer selecting one of the sets of n input/output terminals for coupling to the common data interface for providing access to the first and second memory arrays organized as a (r×((m/r)+(q/r))×n) memory array.
8 more elements
A method of organizing a memory array having m memory locations for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed, the method comprising:
- organizing the m memory locations into first and second non-overlapping memory sub-arrays, the first memory sub-array organized as a (r×t) memory array accessible through a first of the plurality of memory ports and the second memory sub-array organized as a (s×t) memory sub-array accessible through a second of the plurality of memory ports, ((r·t)+(s·t)) equal to m and both r and s multiples of a value q;
- and
- organizing the m memory locations into a common memory array organized as a (q×((r/q)+(s/q))×t) memory array accessible through the common memory interface.
A method of accessing a multi-port memory having a common memory interface and a plurality of memory ports through which a memory array having m memory locations is accessed, the method comprising:
- accessing through a first of the plurality of memory ports (r·t) memory locations of the m memory locations, the (r·t) memory locations organized as a (r×t) memory sub-array;
- accessing through a second of the plurality of memory ports (s·t) memory locations of the m memory locations, the (s·t) memory locations organized as a (s×t) memory sub-array, the sum of (r·t) and (s·t) equal to m, and r and s multiples of a value q;
- and
- accessing through the common memory interface the m memory locations organized as a (q×((r/q)+(s/q))×t) memory array.
1 more element
Dependencies are inferred from the claim text.