Flash memory array structure suitable for multiple simultaneous operations
AssigneeAplus Flash Technology, Inc.
InventorsFu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao
Life of this patent
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Abstract
In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.
Claims9
A memory means for simultaneous memory operations, comprising:
- a) a partitioning means for subdividing a memory into a plurality of sectors containing a plurality of memory cells,
- b) a word line means, a source line means, a sub bit line means and a main bit line means for conditioning cells of said memory for memory operations,
- c) a sector decoder means for coupling said main bit lines to said sub bit lines in said sector,
- d) a multiple input and output means for said sector decoder to couple a plurality of sub bit lines within said sector to a plurality of said main bit lines,
- e) said sector decoder means drives a first set of selector pates to couple main bit lines to a first set of sub bit lines for a write operation and said selector decoder means drives a second set of selector gates to couple main bit lines to a second set of sub bit lines for a read operation to perform a first memory operation in a first sector while performing a second memory operation in a second sector.
Dependencies are inferred from the claim text.