Flash memory array structure suitable for multiple simultaneous operations
AssigneeAplus Flash Technology, Inc.
InventorsFu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao
Life of this patent
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Abstract
In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.
Claims6
A method of simultaneous memory operations, comprising:
- a) partitioning an array of memory cells into a plurality of sectors arranged in rows and columns,
- b) selecting a first memory cells and performing a first memory operation by applying a first set of voltages to a first word line, a first source line, and a first main bit line, and coupling a first sub bit line to said first main bit line controlled by a sector decoder,
- c) selecting a second memory cell and performing a second memory operation, simultaneous to said first memory operation, by applying a second set of voltages to a second word line, a second source line and a second main bit line, and coupling a second sub bit line to said second main bit line controlled by said sector decoder.
Dependencies are inferred from the claim text.