High voltage pulse method and apparatus for digital multilevel non-volatile memory integrated system

A system for generating a pulsed high voltage signal, the system comprising:

• a reference current generator,
• a first voltage to current converter coupled to the reference current generator for generating a first current,
• a second voltage to current converter coupled to the reference current generator for generating a second current, the second current being adjustable,
• a summing circuit coupled to the first and second voltage to current converters to generate a summed current in response to the first and second currents;
• a current to voltage converter coupled to the summing circuit to generate a first high voltage signal in response to the summed current;
• and
• an operational amplifier coupled to the current to voltage converter to generate a second high voltage signal in response to the first high voltage signal.

A system for generating a pulsed signal, the system comprising:

• a bias current generator for generating a plurality of bias currents;
• a high voltage level generator generating a first high voltage signal in response to at least one of the bias currents;
• and
• an operational amplifier having a first input coupled to the high voltage level generator, having an output for generating a pulsed shaped high voltage signal, and having a second input for receiving the pulsed shaped high voltage signal.

A memory system comprising:

• a plurality of memory cells, each memory cell being configurable to store one of a plurality of signal levels being stored in accordance with programming signals;
• and
• a supply source for generating said programming signals in response to a pulsed shaped high voltage signal, the supply source including:
• a bias current generator for generating a plurality of bias currents;
• a high voltage level generator generating a first high voltage signal in response to at least one of the bias currents;
• and
• an operational amplifier having a first input coupled to the high voltage level generator, having an output for generating the pulsed shaped high voltage signal, and having a second input for receiving the pulsed shaped high voltage signal.

A ramp down control circuit comprising:

• a first transistor of a first type including a first terminal, including a second terminal, including a channel between the first and second terminals, and including a gate for controlling current in said channel in response to a power signal;
• a first transistor of a second type including a first terminal for coupling to an output of an operational amplifier, including a second terminal coupled to the first terminal of the first transistor of the first type, including a channel between the first and second terminals, and including a gate for controlling current in said channel in response to the power signal
• a second transistor of a first type including a first terminal coupled to second terminal of the first transistor of the first type, including a second terminal coupled to a ground terminal, including a channel between the first and second terminals, and including a gate for controlling current in said channel;
• a third transistor of a first type including a first terminal, including a second terminal coupled to the ground terminal, including a channel between the first and second terminals, and including a gate for controlling current in said channel in response to a first bias signal;
• a fourth transistor of a first type including a first terminal coupled to the gate of the third transistor of the first type, including a second terminal coupled to the ground terminal, including a channel between the first and second terminals, and including a gate for controlling current and coupled to said first terminal;
• a first capacitor including a first terminal coupled to the first terminal of the first transistor of the second type and including a second terminal;
• a second capacitor including a first terminal coupled to the second terminal of the first capacitor and including a second terminal coupled to the gate of the second transistor of the first type;
• a fifth transistor of a first type including a first terminal coupled to the gate of the first transistor of the first type, including a second terminal coupled to the second terminal of the first capacitor, including a channel between the first and second terminals, and including a gate for controlling current in said channel and coupled to said first terminal;
• a second transistor of the second type including a first terminal coupled to the power signal, including a second terminal coupled to the gate of the second transistor of the first type, including a channel between the first and second terminals, and including a gate for controlling current in said channel;
• and
• a third transistor of the second type including a first terminal coupled to the power signal, including a second terminal coupled to a common node formed of the gate of the second transistor of the second type and the first terminal of the third transistor of the first type, including a channel between the first and second terminals, and including a gate for controlling current in said channel and coupled to said first terminal.

A ramp up control circuit comprising:

• a first transistor of a first type including a first terminal for coupling to a first input of an operational amplifier, including a second terminal, including a channel between the first and second terminals, and including a gate for controlling current in said channel in response to a power signal;
• a second transistor of a first type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal coupled to a ground terminal, including a channel between the first and second terminals, and including a gate for controlling current in said channel;
• a third transistor of a first type including a first terminal coupled to the gate of the second transistor of the first type, including a second terminal coupled to the ground terminal, including a channel between the first and second terminals, and including a gate for controlling current in said channel in response to a first bias signal;
• a fourth transistor of a first type including a first terminal coupled to the gate of the third transistor of the first type, including a second terminal coupled to the ground terminal, including a channel between the first and second terminals, and including a gate for controlling current and coupled to said first terminal;
• a first capacitor including a first terminal coupled to the first terminal of the first transistor of the first type and including a second terminal;
• a second capacitor including a first terminal coupled to the second terminal of the first capacitor and including a second terminal coupled to the gate of the second transistor of the first type;
• and
• a fifth transistor of a first type including a first terminal for receiving the first bias signal, including a second terminal coupled to the ground terminal, including a channel between the first and second terminals, and including a gate for controlling current in said channel in response to a power down signal.

A high voltage generator comprising:

• a charge pump for generating a high voltage pump signal in response to a supply voltage and timing control signals;
• and
• a plurality of supply regulators, each supply regulator generating an output high voltage signal, each high voltage supply regulator comprising a first circuit for buffering an applied high voltage signal and including a push pull source follower for regulation, an operational amplifier for controlling said voltage regulation, a bias circuit for controlling an input voltage in response to said applied high voltage signal,
• wherein the applied high voltage signal applied to one of said high voltage regulators being the high voltage pump signal and the applied high voltage signal applied to others of said high voltage regulators being one of the output high voltage signals.