ROM embedded DRAM with bias sensing
AssigneeMicron Technology, Inc.
InventorsScott Derner, Casey Kurth, Phillip G. Wald
Life of this patent
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Abstract
A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.
Claims30
A memory device comprising:
- a plurality of memory cell capacitors, wherein a portion of the plurality of memory cell capacitors are programmed in a non-volatile manner to a first data state;
- digit lines selectively couplable to the plurality of memory cell capacitors;
- sense circuitry coupled to the digit lines;
- and
- a reference cell coupled to the sense circuitry to force a detection of a second data state in an absence of a programmed memory cell capacitor coupled to the digit lines.
A read only memory (ROM) embedded dynamic random access memory (DRAM) device comprising:
- a plurality of DRAM cell capacitors, wherein a portion of the plurality of DRAM cell capacitors are programmed as ROM cells in a non-volatile manner to a first data state;
- first and second digit lines, the first digit line is selectively couplable to the ROM cells;
- sense circuitry coupled to the first and second digit lines;
- and
- a reference cell coupled to the sense circuitry to force a detection of a second data state in an absence of a programmed memory cell capacitor coupled to the digit lines.
A memory device, comprising:
- a plurality of memory cell capacitors, wherein a portion of the plurality of memory cell capacitors are programmed in a non-volatile manner to a first data state;
- digit lines selectively couplable to the plurality of memory cell capacitors;
- sense circuitry coupled to the digit lines;
- and
- a non-volatile memory cell coupled to the sense circuitry to force a detection of a second data state in an absence of a programmed memory cell capacitor coupled to the lines.
A method of reading a read-only memory (ROM) cell comprising:
- coupling a ROM cell to a first digit line, wherein the ROM cell is a DRAM capacitor cell hard programmed in a non-volatile manner to a first voltage level;
- coupling a reference cell to the first digit line;
- and
- comparing a voltage of the first digit line to a voltage of a second digit line.
A method of reading a read-only memory (ROM) cell comprising:
- coupling a ROM cell to a first digit line, wherein the ROM cell is a DRAM capacitor cell hard programmed in a non-volatile manner to a first voltage level;
- coupling a reference cell to a second digit line;
- and
- comparing a voltage of the first digit line to a voltage of the second digit line.
A method of reading a read-only memory (ROM) cell comprising:
- coupling a first ROM cell to a first digit line, wherein the first ROM cell is a DRAM capacitor cell hard programmed in a non-volatile manner to a first voltage level;
- coupling a second ROM cell to the first digit line;
- and
- comparing a voltage of the first digit line to a voltage of a second digit line.
A method of reading a read-only memory (ROM) cell comprising:
- coupling a ROM cell to a first digit line, wherein the ROM cell is a memory cell capacitor hard programmed in a non-volatile manner to a first voltage level;
- coupling a bias circuit to a second digit line;
- and
- comparing a voltage of the first digit line to a voltage of the second digit line.
A read only memory (ROM) array, comprising:
- a first and a second digit line selectively couplable to a plurality of memory cell capacitors, wherein a portion of the plurality of memory cell capacitors are programmed in a non-volatile manner to a first data state;
- a differential voltage sense amplifier circuit, each of the first and the second digit lines connected to the sense amplifier circuit;
- and
- a first and second reference memory cell, each digit line selectively couplable to one of the first or the second reference memory cell to provide a differential between the digit lines.
A method of reading a read-only memory (ROM) cell, comprising:
- equilibrating first and second digit lines to a common voltage;
- activating a memeory cell word line for coupling a memory cell capacitor to a select one of the first and second digit lines, the memory cell capacitor being programmed in a non-volatile manner to a first data state;
- coupling a reference cell to the second digit line;
- and
- comparing a voltage on the first digit line to a voltage on the second digit line.
Dependencies are inferred from the claim text.