Memory device and operation thereof
AssigneeMacronix International Co., Ltd.
InventorsJen-Ren Huang, Ming-Hung Chou, Hsin-Chien Chen
Life of this patent
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Abstract
A semiconductor memory device is provided, including one or more bit lines, one or more word lines, and a dummy word line, which is coupled to a positive bias. A memory cell and dummy cell are coupled to a bit line and may be coupled to a word line and dummy word line respectively. Coupling the dummy word line to a positive bias at least during an erase operation prevents the dummy cells from being over-erased, which occurs when the dummy word line is coupled to ground.
Claims17
A semiconductor memory device, comprising:
- a memory cell;
- a dummy word line arranged at an edge of a memory array coupled to the memory cell;
- a control logic for supplying a positive bias to the dummy word line during an erase operation;
- and
- at least one bit line coupled to the memory cell.
A semiconductor memory array, comprising:
- a memory cell;
- at least one bit line arranged in a first direction and coupled to the memory cell;
- and
- at least one dummy word line arranged at an edge of a memory array arranged in a second direction perpendicular to the at least one bit line and coupled to the memory cell,
- wherein a positive bias is selectively supplied to the at least one dummy word line at least during erase operation.
A method of forming a semiconductor memory device, comprising:
- coupling a bit line to a memory cell;
- providing a dummy word line at an edge of a memory array;
- coupling the dummy word line to the memory cell;
- and
- supplying a positive bias to the dummy word line.
Dependencies are inferred from the claim text.