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US 6,788,601 B2Granted
Semiconductor memory device and current mirror circuit
AssigneeKabushiki Kaisha Toshiba
InventorsYoshinori Takano, Shigeru Atsumi, Toru Tanzawa
Life of this patent
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Abstract
A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.
Claims16
A semiconductor memory device, comprising:
- an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current;
- a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from said array of memory cells with a reference voltage applied to a reference sense line to determine said data;
- and
- a reference voltage generator configured to generate said reference voltage applied to said reference sense line, said reference voltage generator including:
- a reference cell unit containing a reference cell to flow a reference current as a reference for determination of data in said memory cell, and a first current source load to supply a current to said reference cell;
- a reference transistor unit containing a reference transistor to flow a current reflecting said reference current, and a second current source load to supply a current to said reference transistor;
- a control amp having a first input terminal connected to a first connection node between said reference cell and said first current source load, a second input terminal connected to a second connection node between said reference transistor and said second current source load, and an output terminal connected to a gate of said reference transistor to negative feedback control said reference transistor;
- a current source transistor having a gate commonly connected to said gate of said reference transistor, and a drain connected to said reference sense line from said sense amp;
- and
- a third current source load connected to said reference sense line.
7 more elements
A semiconductor memory device, comprising:
- an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current;
- a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from said array of memory cells with a reference voltage applied to a reference sense line to determine said data;
- and
- a reference voltage generator configured to generate said reference voltage applied to said reference sense line, said reference voltage generator including:
- a reference cell unit containing a reference cell to flow a reference current as a reference for determination of data in said memory cell, and a first current source load connected to an internal boosted-voltage source to supply a current to said reference cell;
- a reference transistor unit containing a reference transistor to flow a current reflecting said reference current, and a second current source load connected to said internal boosted-voltage source to supply a current to said reference transistor, said reference transistor having a gate connected to a connection node between said second current source load and said reference transistor;
- a current source transistor having a gate commonly connected to said gate of said reference transistor, and a drain connected to said reference sense line from said sense amp;
- and
- a third current source load connected to said reference sense line to supply a current to said current source transistor.
6 more elements
A current mirror circuit, comprising:
- a first current path containing a reference current source transistor given a certain gate bias to flow a reference current, and a first current source load connected to a drain of said reference current source transistor;
- a second current path containing a reference transistor to flow a current in response to said reference current, and a second current source load connected to a drain of said reference transistor;
- a control amp having a first input terminal connected to said drain of said reference transistor, a second input terminal connected to said drain of said reference current source transistor, and an output terminal connected to a gate of said reference transistor to negative feedback control said reference transistor;
- and
- an output current source transistor having a gate commonly connected to said gate of said reference transistor.
2 more elements
Dependencies are inferred from the claim text.