Non-volatile semiconductor memory

A non-volatile semiconductor memory device, comprising:

• a plurality of first main bit lines and a plurality of second main bit lines;
• a plurality of first sub bit line groups, each first sub bit line group including a plurality of first sub bit lines corresponding to one of the plurality of first main bit lines;
• a plurality of second sub bit line groups, each second sub bit line group including a plurality of second sub bit lines corresponding to one of the plurality of second main bit lines;
• each of the first sub bit lines and second sub bit lines are connected to a plurality of memory cells;
• a first global bit line coupled to one of the first main bit lines and to one of the second main bit lines;
• a second global bit line coupled to another one of the first main bit lines and another one of the second main bit lines;
• a first sense amplifier coupled to the first global bit line;
• and
• a second sense amplifier coupled to the second global bit line.