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US 6,788,593 B2Granted
Asynchronous, high-bandwidth memory component using calibrated timing elements
AssigneeRambus Inc.
InventorsFrederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark
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Abstract
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
Claims55
A memory device comprising:
- one or more address registers that load a received memory address at a time indicated by a received input load signal;
- one or more delay elements that asynchronously generate a data register load signal at a predetermined time after the received input load signal;
- and
- one or more data registers that load memory data at a time indicated by the data register load signal,
- wherein the one or more delay elements are calibrated to a reference generated within the memory device.
2 more elements
A memory device comprising:
- one or more address registers that load a received memory address at a time indicated by a received input load signal;
- an output bus;
- and
- one or more delay elements that asynchronously generate a data enable signal at a predetermined time after the received input load signal to present read data on the output bus,
- wherein the one or more delay elements are calibrated in response to one or more signals received from a source external to the memory device.
2 more elements
A memory device comprising:
- a memory array that is accessed by sensing a memory row and then accessing one or more memory columns of the sensed memory row;
- a plurality of delay elements that are responsive to input load signals to produce corresponding sequences of asynchronously timed register load signals;
- a sequence of address registers that receive addresses and that advance the addresses through the address registers in response to the sequences of asynchronously timed register load signals;
- and
- wherein the memory array is responsive to addresses that have advanced through the sequence of address registers.
2 more elements
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals;
- and
- concurrently pipelining the plurality of memory access operations.
1 more element
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals;
- wherein asynchronously pipelining comprises:
- asynchronously advancing data of each memory operation through a plurality of pipeline registers.
1 more element
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals;
- wherein asynchronously pipelining comprises:
- asynchronously advancing address data of each memory operation through a plurality of pipeline registers.
1 more element
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals;
- concurrently pipelining the plurality of memory access operations;
- wherein asynchronously pipelining comprises asynchronously advancing data of each memory operation through a plurality of pipeline registers.
1 more element
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals;
- for each memory access initiation signal, successively and asynchronously delaying the memory access initiation signal to produce a corresponding sequence of asynchronously timed pipeline signals that control said pipelining.
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals;
- for each memory access initiation signal, successively and asynchronously delaying the memory access initiation signal to produce a sequence of asynchronously timed pipeline signals;
- wherein said pipelining comprises signaling pipeline registers with the asynchronously timed pipeline signals.
1 more element
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals;
- producing delays in the memory device with matching delay elements, wherein the matching delay elements are collectively adjustable.
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals;
- producing delays in the memory device with sets of matching delay elements, wherein the matching delay elements are collectively adjustable,
- periodically calibrating the matching delay elements with reference to an externally supplied timing reference.
1 more element
Dependencies are inferred from the claim text.