System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch

A dynamic random access memory array architecture, comprising:

• a plurality of bit-line pairs coupled to a fan-in node, said plurality of bit-line pairs each including a true bit-line and a complementary bit-line coupled to one or more memory storage cells associated with the memory array;
• a sense amplifier coupled to each of said plurality of bit-line pairs, said sense amplifier configured to amplify a small voltage difference between an associated true and complementary bit-line to a full level signal at predetermined high and low logic voltage levels;
• and
• a plurality of bit-switch pairs associated with each bit-line pair, said bit-switch pairs for selectively coupling said bit-line pairs and said sense amplifiers to said fan-in node, each said bit-switch pair further configured so as to couple said fan-in node to said bit-line pair associated therewith prior to the activation of a word-line associated with a selected cell for a write operation thereto, thereby commencing said write operation to said selected cell prior to the completion of time associated with signal development on said bit-line pair.

A method for implementing a direct write operation to a selected storage cell of a dynamic random access memory (DRAM) device, the method comprising:

• activating a bit-switch pair so as to couple a bit-line pair to a fan-in node prior to activation of a word-line associated with the selected storage cell;
• and
• said bit-line pair comprising a true bit-line and a complementary bit-line coupled to a sense amplifier, said sense amplifier configured to amplify a small voltage difference between said true and complementary bit-lines to a full level signal at predetermined high and low logic voltage levels;
• wherein once the word-line associated with the selected storage cell is activated, the write operation to the selected cell is commenced, prior to the completion of time associated with signal development on said true and complementary bit-lines.