Bitline reference voltage circuit
AssigneesUnited Memories, Inc., Sony Corporation
InventorsMichael C. Parris, Kim C. Hardee
Life of this patent
Estimating the term…
Abstract
A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.
Claims20
A bitline reference voltage circuit for an integrated circuit memory comprising:
- a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal;
- a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal;
- a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal;
- and
- a capacitor coupled between the intermediate node and the source of constant voltage.
A bitline reference voltage circuit for an integrated circuit memory comprising:
- a first plurality of transistors having current paths respectively coupled between a first plurality of bitlines and an intermediate node, and a plurality of gates coupled together for receiving a first control signal;
- a second plurality of transistors having current paths respectively coupled between a second plurality of bitlines and the intermediate node, and a plurality of gates coupled together for receiving a second control signal;
- a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal;
- and
- a capacitor coupled between the intermediate node and the source of constant voltage.
Dependencies are inferred from the claim text.