Programmable latch circuit inserted into write data path of an integrated circuit memory
AssigneeProMOS Technologies Inc.
InventorJon Allan Faue
Life of this patent
Estimating the term…
Abstract
A latch circuit and method of operation improves the performance of an integrated circuit memory by adding an extra latch into the write data path. The added latch is programmable such that it either is disabled (allowing the transparent flow of data), or enabled (data flow is inhibited by extra clock). In areas of the chip where the address/control information is fast, but the data is slow, the latch is disabled to allow the data to flow as fast as possible. In areas of the chip where the address/control information is slow, but the data is fast, the latch is enabled such that data cannot flow freely and must be gated by clock information.
Claims19
An integrated circuit memory comprising an extra latch inserted into at least one write path of the memory comprising:
- means for aligning address/control information with corresponding data;
- and
- means for disabling the latch in areas of the integrated circuit where the address/control information is fast, but the data is slow, to allow free data flow.
An integrated circuit memory comprising:
- a plurality of write paths for writing data into a memory array;
- a plurality of latches, one of the latches inserted into each corresponding write path;
- and
- means for programming the plurality of latches to prevent corruption of the data for a given address (Y) by ensuring that data for the next address (Y+1) does not arrive too soon.
A latch circuit for a write data path in an integrated circuit memory comprising:
- a transfer gate having a data input for receiving global data, a data output for providing local data, and a control input;
- a logic circuit having a first input for receiving a clock signal, a second input for receiving a programming signal, and an output coupled to the control input of the transfer gate;
- and
- a cross-coupled latch coupled to the data output of the transfer gate.
A method of operating an integrated circuit memory comprising:
- inserting an extra latch into at least one write path of the memory including means for aligning address/control information with corresponding data;
- and
- disabling the latch in areas of the integrated circuit where the address/control information is fast, but the data is slow, to allow free data flow.
A method of operating an integrated circuit memory including a plurality of write paths for writing data into a memory array, the method comprising:
- inserting a plurality of latches, one into each corresponding write path;
- and
- programming the plurality of latches to prevent corruption of the data for a given address (Y) by ensuring that data for the next address (Y+1) does not arrive too soon.
An integrated circuit memory comprising an extra latch inserted into at least one write path of the memory comprising:
- means for aligning address/control information with corresponding data;
- and
- means for enabling the latch in areas of the integrated circuit where the address/control information is slow, but the data is fast, to prevent data from flowing freely.
A method of operating an integrated circuit memory comprising:
- inserting an extra latch into at least one write path of the memory including means for aligning address/control information with corresponding data;
- and
- enabling the latch in areas of the integrated circuit where the address/control information is slow, but the data is fast, to prevent data from flowing freely.
Dependencies are inferred from the claim text.