Asynchronous semiconductor memory device
AssigneeFujitsu Limited
InventorsKenji Nagai, Hirokazu Nagashima
Life of this patent
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Abstract
An asynchronous semiconductor memory device includes an output circuit, which outputs data read from a memory unit, and a high impedance control circuit. The high impedance circuit is connected to the output circuit, stores a burst completion address, and compares a present address with the burst completion address. The high impedance control circuit causes a data output terminal of the output circuit to enter a high impedance state when the present address substantially coincides with the burst completion address. Due to the high impedance control circuit, an exclusive terminal for high impedance control is not necessary.
Claims33
An asynchronous semiconductor memory device comprising:
- a memory unit;
- an output circuit for outputting data read from the memory unit;
- and
- an output control circuit connected to the output circuit for storing read completion information and comparing present read operation information with the read completion information, wherein the output control circuit causes the output circuit to enter a disconnected state when the present read operation information substantially coincides with the read completion information.
A method for controlling an output circuit that outputs data read from a memory unit of an asynchronous semiconductor memory, the method comprising the steps of:
- storing read completion information;
- comparing present read operation information with the read completion information;
- and
- causing the output circuit to enter a disconnected state when the present read operation information substantially coincides with the read completion information.
A memory system comprising:
- an asynchronous semiconductor memory device;
- and
- a controller for controlling the semiconductor memory device, wherein the controller provides data read completion information of data to the semiconductor memory device, the semiconductor memory device including;
- a memory unit;
- an output circuit for outputting data read from the memory unit;
- and
- an output control circuit connected to the output circuit for storing read completion information and comparing present read operation information with the read completion information, wherein the output control circuit causes the output circuit to enter a disconnected state when the present read operation information substantially coincides with the read completion information.
Dependencies are inferred from the claim text.