Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same

A memory device, comprising:

• an output buffer, that includes:
• a first line set at a first potential and a second line set at a second potential;
• a first transistor and a second transistor connected in series between the first line and the second line, and having an intermediate node connected to an output of said output buffer;
• and
• means for unidirectionally decoupling the output of said output buffer from one of said first and second lines during a switching transient of the output buffer, the decoupling means arranged in series with said first and second transistors between said first and second lines.

A method, comprising:

• inputting a first logic value to an input of an output buffer;
• inputting a second logic value, different from the first value, to the input;
• and
• unidirectionally decoupling an output of the output buffer from a line at a first potential during a switching transient of the output buffer.

A device, comprising:

• a first line at a first potential;
• a second line at a second potential;
• first and second switches coupled in series between the first and second lines, and defining, between the first and second switches, an output node;
• a diode coupled between the output node and the first line;
• and
• a third switch coupled in parallel to the diode, the third switch configured to close at an end of a switching transient of the device.

A device, comprising:

• a first line at a first potential;
• a second line at a second potential;
• first and second switches coupled in series between the first and second lines, and defining, between the first and second switches, an output node;
• and
• a threshold lowering diode coupled in series between the first line and the output node, the threshold lowering diode having a first transistor coupled between first and second terminals of the threshold lowering diode, a second transistor in diode configuration coupled between the second terminal and a control terminal of the first transistor, and a current generator having an output coupled to the control terminal of the first transistor.