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US 6,788,585 B1Granted
System and method for processing data in a memory array
AssigneeCisco Technology, Inc.
InventorsJohn K. Eitrheim, Jeffrey A. Huxel
Life of this patent
Estimating the term…
Abstract
A method for processing data is provided that includes receiving a first request in a first clock cycle from a processor for access to a first data segment corresponding to a first address included in the first request. A second request for access to a second data segment corresponding to a second address included in the second request is received during a second clock cycle. The second data segment is disabled from being communicated to the processor and the first data segment is communicated to the processor in response to the second request.
Claims28
An apparatus for processing data in a memory array, comprising:
- a processor operable to generate a plurality of instructions for processing data;
- and
- a memory array coupled to the processor and operable to store data that may be communicated to the processor, the memory array operable to receive a first request in a first clock cycle from the processor for access to a first data segment corresponding to a first address included in the first request, the memory array operable to respond to the first request by communicating the first data segment to the processor, the memory array being further operable to receive a second request in a second clock cycle for access to a second data segment corresponding to a second address included in the second request, the memory array operable to respond to the second request by allowing the second data segment to be read out of the memory array and onto a bit line, the memory array operable to prevent the second data segment from propagating to the processor during the second clock cycle and to allow the first data segment to be communicated to the processor in response to the second request.
A method for processing data, comprising:
- receiving a first request from a processor for access to a first data segment corresponding to a first address included in the first request, the first request being received during a first clock cycle;
- receiving a second request for access to a second data segment corresponding to a second address included in the second request, the second request being received during a second clock cycle;
- disabling the second data segment from being communicated to the processor;
- and
- communicating the first data segment to the processor in response to the second request.
2 more elements
A system for processing data in a memory array, comprising:
- a processor operable to generate a plurality of instructions for processing data;
- and
- a memory array coupled to the processor and operable to store data that may be communicated to the processor, the memory array receiving a first request from the processor for access to a first data segment corresponding to a first address included in the first request, the first request being received during a first clock cycle, the memory array being further operable to receive a second request for access to a second data segment corresponding to a second address included in the second request, the second request being received during a second clock cycle, wherein the memory array does not enable the second data segment to propagate from the memory array such that the first data segment is communicated to the processor in response to the second request, the memory array further comprising:
- a sense amplifier operable to enable a selected one of the first and second data segments to propagate from the memory array to the processor;
- an address decoder operable to receive the first and second requests and to decode the first and second addresses in order to access the first and second data segments;
- and
- a column multiplexer operable to receive a plurality of sets of bit lines and to communicate with the address decoder in order to execute multiplexing such that a resultant is produced and communicated to the sense amplifier.
4 more elements
A system for processing data, comprising:
- means for receiving a first request from a processor for access to a first data segment corresponding to a first address included in the first request, the first request being received during a first clock cycle;
- means for receiving a second request for access to a second data segment corresponding to a second address included in the second request, the second request being received during a second clock cycle;
- means for disabling the second data segment from being communicated to the processor;
- and
- means for communicating the first data segment to the processor in response to the second request.
2 more elements
A computer readable medium having code for processing data, the code operable to:
- receive a first request from a processor for access to a first data segment corresponding to a first address included in the first request, the first request being received during a first clock cycle;
- receive a second request for access to a second data segment corresponding to a second address included in the second request, the second request being received during a second clock cycle;
- disable the second data segment from being communicated to the processor;
- and
- communicate the first data segment to the processor in response to the second request.
2 more elements
Dependencies are inferred from the claim text.