US 6,788,583 B2 · Pre-charge method for reading a non-volatile memory cell

Abstract

A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

Claims19

Dependent claims

A method of detecting a charge stored on a source charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells, the method comprising:

grounding a first bit line that forms a source junction with a channel region of the first memory cell, the channel region being to the right of the first bit line;
applying a high voltage to a gate of the first memory cell;
applying a high voltage toga second bit line that forms a drain junction with the channel region, the second bit line positioned to the right of the first bit line and to the right of the channel region;
isolating a third bit line such that its potential is effected only by its junctions with a second channel region and a third channel region;
the third bit line being to the right of the second bit line and separated from the second bit line only by the second channel region that is positioned there between;
the third channel region being positioned to the right of the third bit line;
applying a high voltage to a pre-charge bit line, the pre-charge bit line being to the right of the third bit line;
and
detecting current flow at the second bit line.

6 more elements

A method of detecting a charge stored in a charge storage region adjacent to a first bit line within an array of dual bit dielectric memory cells, the method comprising:

applying a positive voltage bias to a second bit line with respect to the first bit line, the second bit line being separated from the first bit line only by a first channel region positioned beneath the charge storage region;
applying a positive voltage bias to a word line with respect to the first bit line, the word line being positioned over the first channel region;
applying a neutral voltage bias to a pre-charge bit line with respect to the second bit line, the pre-charge bit line being separated from the second bit line by:
a second channel region that is adjacent to the second bit line;
a third bit line that is adjacent to the second channel region;
a third channel region that is adjacent to the third bit line;
a fourth bit line that is adjacent to the third channel region;
and
a fourth channel region that is adjacent to the fourth bit line;
isolating the third bit line such that its potential is effected only by its junctions with each of the second channel region and the third channel region;
isolating the fourth bit line such that its potential is effected only by its junctions with each of the third channel region and the fourth channel region;
and
detecting current flow at the second bit line.

10 more elements

An array of dual bit dielectric memory cells, the array comprising:

a first bit line of a first conductivity semiconductor;
a first channel region of an opposite conductivity semiconductor forming a junction with the first bit line;
a charge storage layer positioned above the first channel region and separated from the first channel region by a first insulating barrier;
a word line forming a gate positioned over the charge storage layer and separated from the charge storage layer by a second insulating barrier;
a second bit line of the first conductivity semiconductor positioned to the right of the channel region and forming a junction with the channel region;
a second channel region of the first conductivity semiconductor and positioned to the right of the second bit line and forming a junction with the second bit line;
a third bit line of the first conductivity semiconductor and positioned to the right of the second channel region and forming a junction with the second channel region;
a third channel region of the opposite conductivity semiconductor and positioned to the right of the third bit line and forming a junction with the third bit line;
a pre-charge bit line of the first conductivity semiconductor and positioned to the right of the third channel region;
a word line control circuit for applying a high voltage to the gate;
a bit line control circuit for:
coupling the first bit line to ground;
applying a high voltage to the second bit line;
isolating the third bit line such that its potential is effected only by its junctions with the second channel region and the third channel region;
applying a high voltage to the pre-charge bit line;
and
a current sensor circuit for detecting the state of a charge stored in the charge storage layer by detecting current flow at the second bit line.

14 more elements

An array of dual bit dielectric memory cells, the array comprising:

a first bit line of a first conductivity semiconductor;
a first channel region of an opposite conductivity semiconductor forming a junction with the first bit line;
a charge storage layer positioned above the first channel region and separated from the first channel region by a first insulating barrier;
a word line forming a gate positioned over the charge storage layer and separated from the charge storage layer by a second insulating barrier;
a second bit line of the first conductivity semiconductor and positioned to the right of the channel region and forming a junction with the channel region;
a second channel region;of the opposite conductivity semiconductor and positioned to the right of the second bit line and forming a junction with the second bit line;
a third bit line of the first conductivity semiconductor and positioned to the right of the second channel region and forming a junction with the second channel region;
a third channel region of the opposite conductivity semiconductor and positioned to the right of the third bit line and forming a junction with the third bit line;
a pre-charge bit line of the first conductivity semiconductor and positioned to the right of the third channel region;
a current sensor circuit for detecting the state of a charge stored in the charge storage layer by detecting current flow at the second bit line;
a voltage control circuit for:
applying a positive voltage bias to the second bit line with respect to the first bit line;
applying a positive voltage bias to the word line with respect to the first bit line;
applying a neutral voltage bias to the pre-charge bit line with respect to the second bit line;
and
isolating the third bit line such that its potential is effected only by its junctions with each of the second channel region and the third channel region.

13 more elements

Dependencies are inferred from the claim text.

Pre-charge method for reading a non-volatile memory cell

Life of this patent

Pre-charge method for reading a non-volatile memory cell

Life of this patent

Abstract

Claims19