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US 6,788,581 B2Granted
Non-volatile semiconductor memory device configured to reduce rate of erroneously reading data from memory cell
AssigneeRenesas Technology Corp.
InventorMasaaki Mihara
Life of this patent
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Abstract
A transistor operating as a current source supplying a memory cell with a current is configured to operate in a saturation range when a node subjected to a decision as to whether a memory cell has a high or low level has a voltage in a range of no more than a threshold voltage.
Claims8
A non-volatile semiconductor memory device comprising:
- a plurality of memory cells;
- a data line arranged to be electrically coupled with a single cell selected from said plurality of memory cells in a data read operation;
- a sense amplifier circuit for detecting a current of said data line in said data read operation, said sense amplifier circuit including a first current source for supplying said data line with a current in said data read operation, said first current source having a first internal node arranged to be connected to said data line in said data read operation and a first transistor arranged to be electrically coupled between said first internal node and a power supply voltage, said sense amplifier circuit further including a first conversion circuit for comparing a voltage of said first internal node with a first threshold voltage;
- and
- a first voltage setting circuit for setting a voltage of a gate of said first transistor to operate said first transistor in a saturation range when said first internal node has a voltage in a range of no more than said first threshold voltage.
2 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of memory cells;
- a data line arranged to be electrically coupled with a single cell selected from said plurality of memory cells in a data read operation;
- a sense amplifier circuit for detecting a current of said data line in said data read operation, said sense amplifier circuit including a first current source for supplying said data line with a current in said data read operation, said first current source having a first internal node arranged to be connected to said data line in said data read operation and a first transistor arranged to be electrically coupled between said first internal node and a power supply voltage;
- a first conversion circuit for comparing a voltage of said first internal node with a first threshold voltage;
- and
- a first voltage setting circuit for setting a voltage of a gate of said first transistor to operate said first transistor in a saturation range when said first internal node has a voltage in a range of no more than said first threshold voltage, wherein
- said first conversion circuit has a second current source for supplying said data line with a current in said data read operation and a current limit circuit for receiving a current from said second current source and limiting the current to a predetermined amount of current;
- said second current source has a second transistor electrically coupled between said first internal node and a power supply voltage;
- and
- said second transistor operates in a saturation range when said first internal node has a voltage in a range of no more than said first threshold voltage.
7 more elements
Dependencies are inferred from the claim text.