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US 6,788,576 B2Granted
Complementary non-volatile memory cell
AssigneeTower Semiconductor Ltd.
InventorYakov Roizin
Life of this patent
Estimating the term…
Abstract
A complimentary non-volatile memory (CNVM) cell includes an n-channel transistor and a p-channel transistor that have drains connected like a CMOS inverter, and that are controlled by a shared floating gate and a shared control gate. The CNVM cell is programmed by band-to-band tunneling (BBT) electrons generated in the source of p-channel transistor, and is erased by BBT holes generated in the source of n-channel transistor (or by back tunneling of electrons from the floating gate). Read out is performed using a select transistor connected to the drains of the n-channel and p-channel transistors.
Claims12
A complementary non-volatile memory cell comprising:
- a p-channel transistor having a source region and a drain region separated by a first channel, the drain region being connected to a node;
- an n-channel transistor having a source region and a drain region separated by second channel, the drain region being connected to the node;
- and
- a select transistor having a first terminal connected to the node, and a second terminal connected to a read bit line,
- wherein the n-channel transistor and the p-channel transistor share a floating gate structure that extends over the first and second channel regions.
2 more elements
A complementary non-volatile memory cell comprising:
- a p-channel transistor having a source region and a drain region separated by a first channel, the drain region being connected to a node;
- an n-channel transistor having a source region and a drain region separated by second channel, the drain region being connected to the node, wherein the n-channel transistor and the p-channel transistor share a floating gate structure that extends over the first and second channel regions;
- a control gate structure located adjacent to the floating gate structure;
- and
- means for applying a positive voltage on the control gate structure and a negative voltage on the source region of the p-channel transistor such that the floating gate structure is programmed by band-to-band tunneling of electrons.
2 more elements
A complementary non-volatile memory cell comprising:
- a p-channel transistor having a source region and a drain region separated by a first channel, the drain region being connected to a node;
- an n-channel transistor having a source region and a drain region separated by second channel, the drain region being connected to the node, wherein the n-channel transistor and the p-channel transistor share a floating gate structure that extends over the first and second channel regions;
- a control gate structure located adjacent to the floating gate structure;
- and
- means for applying a negative voltage on the control gate structure and a positive voltage on the source region of the n-channel transistor such that the floating gate structure is erased.
2 more elements
A complementary non-volatile memory cell comprising:
- a p-channel transistor having a source region and a drain region separated by a first channel, the drain region being connected to a node;
- an n-channel transistor having a source region and a drain region separated by second channel, the drain region being connected to the node, wherein the n-channel transistor and the p-channel transistor share a floating gate structure that extends over the first and second channel regions;
- and
- a control gate structure located adjacent to the floating gate structure,
- wherein the floating gate structure and the control gate structure comprise portions of a single polycrystalline silicon layer such that the control gate structure is formed next to the floating gate structure, and
- wherein the control gate structure comprises a finger portion extending between elongated portions of the floating gate structure.
3 more elements
A complementary non-volatile memory cell comprising:
- a p-channel transistor having a first source and a first drain separated by a first channel;
- an n-channel transistor having a second source and a second drain separated by a second channel;
- a floating gate structure extending over the first channel and the second channel;
- a control gate structure formed adjacent to the floating gate structure;
- a conductor connected between the first drain of the p-channel transistor and the second drain of the n-channel transistor;
- and
- a select transistor having a first terminal connected to the second drain of the n-channel transistor, and a second terminal connected to a read bit line.
4 more elements
A complementary non-volatile memory cell comprising:
- a p-channel transistor having a first source and a first drain separated by a first channel;
- an n-channel transistor having a second source and a second drain separated by a second channel;
- a floating gate structure extending over the first channel and the second channel;
- a control gate structure formed adjacent to the floating gate structure;
- and
- means for applying a positive voltage on the control gate structure and a negative voltage on the source region of the p-channel transistor such that the floating gate structure is programmed by band-to-band tunneling of electrons.
3 more elements
A complementary non-volatile memory cell comprising:
- a p-channel transistor having a first source and a first drain separated by a first channel;
- an n-channel transistor having a second source and a second drain separated by a second channel;
- a floating gate structure extending over the first channel and the second channel;
- a control gate structure formed adjacent to the floating gate structure;
- and
- means for applying a negative voltage on the control gate structure and a positive voltage on the source region of the n-channel transistor such that the floating gate structure is erased.
3 more elements
A complementary non-volatile memory cell comprising:
- a p-channel transistor having a first source and a first drain separated by a first channel;
- an n-channel transistor having a second source and a second drain separated by a second channel;
- a floating gate structure extending over the first channel and the second channel;
- and
- a control gate structure formed adjacent to the floating gate structure,
- wherein the floating gate structure and the control gate structure comprise portions of a single polycrystalline silicon layer such that the control gate structure is formed next to the floating gate structure, and
- wherein the control gate structure comprises a finger portion extending between elongated portions of the floating gate structure.
4 more elements
A method for controlling a non-volatile memory cell including a p-channel transistor, an n-channel transistor, a floating gate structure extending over channel regions of both the p-channel transistor and the n-channel transistor, and a control gate structure located adjacent to the floating gate structure, the method comprising:
- applying a positive voltage on the control gate structure and a negative voltage on a source region of the p-channel transistor such that the floating gate structure is programmed by band-to-band tunneling of electrons, and
- applying a negative voltage on the control gate structure and a positive voltage on the source region of the n-channel transistor such that the floating gate structure is erased by back tunneling of electrons from the floating gate structure to the source region of the n-channel transistor and/or band-to-band hole injection into the floating gate structure.
Dependencies are inferred from the claim text.